Advanced Internet-of-Things (IoT) devices are increasingly used in high-temperature environments, such as automotive, aerospace, defense, and industrial applications. High-temperature voltage references are crucial for these systems. This paper presents two topologies designed for high-temperature operation. The first topology minimizes design costs by using a replica branch to decouple leakage from the core, reducing its impact on the reference voltage. The second topology optimizes the operating temperature by employing one-stage amplifiers as buffers to handle junction leakage while maintaining body voltage. Both designs are fabricated in a 180 nm CMOS process. The first design supports operation up to 140∘C with an average temperature coefficient (TC) of 70 ppm/∘C, while the second design operates up to 170∘C with a TC of 64 ppm/∘C. The designs also exhibit line sensitivities of 0.46 %/V and 0.31 %/V, PSRRs of –37.8 dB and –38.3 dB at 100 Hz, and power consumption of 111 pW and 136.8 pW at room temperature, respectively.

We propose a low-power voltage reference that enables independent adjustment of temperature sensitivity and output level. This design enhances the temperature sensitivity without impacting the output level distribution, in contrast to previous methods. The proposed circuit achieves this by integrating a separate control system that utilizes diode-connected pMOS transistors and an analog multiplexer for output level adjustment, along with biasing current control to improve the temperature sensitivity. In a 180-nm CMOS process, the prototype circuit generates a stable reference voltage averaging 192 mV, maintaining an accuracy of ±8.8 mV ($\pm 3\sigma $) from 0 °C to 75 °C across ten samples. In addition, it consumes only 35.8 pW at 0.6 V and 25 °C.

This brief introduces a compact-size hardware accelerator for dynamic neural fields (DNF) used in object tracking. To address the substantial computational workload and memory occupancy associated with conventional DNFs, three key approaches are implemented: kernel size reduction and abstraction, the replacement of sigmoidal functions with comparison operations, and the approximation of rectangular-shaped objects. The design is realized in a 28-nm CMOS process, resulting in a layout with an area of 0.53 mm2. Simulation results demonstrate that the accelerator processes$256 \times 256$dynamic vision sensor (DVS) frames at 211 frames per second (fps), with a power consumption of 1.68 mW under such conditions.

This brief presents an energy-efficient accelerator for convolutional neural network (CNN) layer computations in a compact system. The accelerator replaces traditional data shift registers with a multiplexer-based barrel shifter, offering greater flexibility for supporting various models and reducing power consumption by 56.2% compared to flip-flop-based shifters. The prototype, fabricated using a 180-nm CMOS process, accelerates CIFAR-10 dataset CNN computations by 8.5 times compared to a system without the accelerator. It achieves this speedup while consuming only$4.7 ~\mu \text{W}$of power and$9.53 ~\mu \text{J}$for each inference task.

We propose a low-power voltage reference of which temperature coefficient (TC) and absolute output level are independently adjustable. It enables to optimize TC without sacrificing output level distribution, compared with the previous works. The design provides the separate control by employing a DAC using diode-connected PFETs and an analog multiplexer for the output level trimming, in addition to biasing current control for TC improvement. Fabricated in a 180 nm CMOS process, the proposed circuit generates a stable reference voltage of 192 mV on average, with a $\pm 3 \sigma$ inaccuracy of 8.8 mV from 0 to $75^{o}\mathrm{C}(10$ samples), while consuming only 35.8 pW at 0.6 V and $25^{o}\mathrm{C}$.

Implementing a neural network (NN) inference in a millimeter-scale system is challenging due to limited energy and storage size. This article proposes an energy-aware adaptive NN inference implementation that utilizes one of two exits with different accuracies and computation options. The early-exit path provides a shorter processing time but less accuracy than the main-exit path. To compensate for the reduced accuracy, it additionally applies the main-exit path if the entropy of the early-exit inference is higher than a predetermined value. The NN is implemented with a custom low-power 180-nm CMOS processor chip and a 90-nm embedded flash memory chip and tested by the CIFAR-10 dataset. The measurement results show that the implemented convolutional NN (CNN) reduces processing time and thus energy consumption by 43.9% compared with a main-exit-only method while sacrificing its accuracy from 69.9% to 66.2%. Also, we explore the required minimum battery capacity at each optimal configuration for accuracy and/or energy consumption to achieve energy-autonomous operation under measured exemplary light profiles. It requires a minimum battery capacity of 855 mJ, acceptable for the target miniature system with two millimeter-scale batteries (684 mJ each). Compared with the state-of-the-art CNN technique (BranchyNet) allowing early stopping, the proposed design improves the accuracy by 0.7% and 3.3% to maintain energy-autonomous operation with two and one millimeter-scale batteries, respectively. Compared with the state-of-the-art lightweight CNN technique (MobileNet), this work provides flexibility with a tradeoff between accuracy and processing time for different application requirements.

This paper describes a miniature edge device that performs neural network inference with different exit options depending on available energy. In addition to the main-exit path, it provides an alternative, early-exit path that requires less computation and thus increase the number of inference operations for given energy. To compensate its degraded accuracy, the proposed device provides entropy as a confidence level for the early exit. The network is implemented with a custom low-power 180 nm CMOS processor chip and a 90 nm embedded flash memory chip and tested by images from CIFAR-10 dataset. The measurement results show the proposed neural network reduces processing time and thus energy consumption by 41.3% compared with the main-exit only method while sacrificing its accuracy from 69.5% to 66.0%.

Each fall, millions of monarch butterflies across the northern US and Canada migrate up to 4,000 km to overwinter in the exact same cluster of mountain peaks in central Mexico. To track monarchs precisely and study their navigation, a monarch tracker must obtain daily localization of the butterfly as it progresses on its 3-month journey. And, the tracker must perform this task while having a weight in the tens of milligram (mg) and measuring a few millimeters (mm) in size to avoid interfering with monarch's flight. This paper proposes mSAIL, 8 × 8 × 2.6 mm and 62 mg embedded system for monarch migration tracking, constructed using 8 prior custom-designed ICs providing solar energy harvesting, an ultra-low power processor, light/temperature sensors, power management, and a wireless transceiver, all integrated and 3D stacked on a micro PCB with an 8 × 8 mm printed antenna. The proposed system is designed to record and compress light and temperature data during the migration path while harvesting solar energy for energy autonomy, and wirelessly transmit the data at the overwintering site in Mexico, from which the daily location of the butterfly can be estimated using a deep learning-based localization algorithm. A 2-day trial experiment of mSAIL attached on a live butterfly in an outdoor botanical garden demonstrates the feasibility of individual butterfly localization and tracking.