With the growing complexity of modern micro-architectures, processor design must accommodate a wide array of parameters, resulting in vast design spaces. Identifying the optimal trade-offs among various design metrics poses a significant challenge. Performance is inherently difficult to model analytically, while area can be represented by analytical models. Performance evaluation relies on expensive and time-consuming cycle-accurate simulators (CAS), which puts forward strict requirements on the convergence speed and data dependence of the optimization methods. In this paper, based on the characteristics of the design metrics, the processor design problem is modeled as a hybrid black-box and white-box multi-objective discrete optimization problem (BWMO-DOP). In engineering applications, parallel simulation is a common acceleration technology. Therefore, white-box objective, area, is formulated as parallel constraints, while black-box objective, performance, is approximated by order-preserving surrogate objective. And then, BWMO-DOP is simplified into parallel single-objective expensive black-box optimization problems, which are solved by an efficient SOP-MOOA. SOP-MOOA iteratively explores more design points, enhancing the accuracy of the surrogate model while simultaneously updating the Pareto set. Experimental results demonstrate that the proposed algorithm outperforms baseline algorithm in an engineering case and three general numerical cases. In the engineering experiment for performance-area optimization, the proposed algorithm outperforms the baseline algorithm by a factor of more than two when considering the combined effect of performance improvement percentage and area reduction percentage. In numerical tests conducted on three 40-dimensional black-box functions under the same evaluation overhead, the proposed algorithm consistently identified Pareto set of superior quality.

Design space exploration (DSE), which aims to optimize the parameter configurations for the processor with a limited evaluation budget, is an important but challenging problem. Processor performance for a given parameter configuration can only be obtained through expensive evaluations. A key characteristic of processor DSE is that the optimization objective is the benchmark score, which is typically computed as a weighted combination of multiple sub-benchmark scores. Each sub-benchmark score can only be obtained through a costly evaluation. Bayesian optimization (BO) is widely used for DSE through an iterative process, where a surrogate model is constructed and updated to guide the selection of parameter configurations in each iteration. However, during the optimization process, it is not always necessary to evaluate all subbenchmarks for every recommended parameter configuration. In some cases, evaluating only a subset of sub-benchmarks can still provide significant improvements to the surrogate model. This paper proposes a BO-based algorithm that effectively utilizes the evaluation budget for efficient optimization. In each iteration, the evaluation budget is divided into two parts: exploitation and exploration. For the exploitation part, we propose a diversity-aware horse racing selection rule and use ordinal optimization to identify configurations with a high likelihood of being optimal. They are evaluated on all sub-benchmarks to obtain the total scores. For the exploration part, we propose a conditional entropy-based greedy algorithm to allocate the evaluation budget across parameter configurations and their corresponding sub-benchmarks, which can effectively improve the surrogate model. We conduct a comprehensive numerical experiment to validate the effectiveness of both components of our algorithm. Furthermore, experiments on three real-world DSE problems demonstrate that our algorithm outperforms state-of-the-art Bayesian optimization methods.

Design Space Exploration (DSE) in processors is an expensive discrete simulation optimization problem. The data requirements of the regular data-driven methods are so large that it is challenging to converge to a satisfactory solution within a limited simulation budget. Based on binary integer linear programming (BILP), an iteratively piecewise linear approximate method (IPLAM) is proposed for this kind of problems to reduce the dependence of simulation data. IPLAM starts from an initial reference point. Each iteration generates a set of trial points based on the most promising reference point by piecewise shift method. After evaluating the trial points, a local surrogate model is constructed for the unit neighborhood of the reference point. The surrogate model is then used to guide the exploration of the next reference point. In theory, IPLAM can converge to the global optimal point under mild assumptions, which is further verified by the numerical experiments. Meanwhile, the numerical experiments demonstrate that IPLAM outperforms the advanced Bayesian optimization and differential evolution methods on high-dimensional discrete black-box test functions. Besides, the practical effectiveness of IPLAM is validated by an industrial case for processor DSE.