Image enhancement serves as a fundamental step in many advanced computer graphics tasks in the field of Internet of Things. However, existing methods often struggle to meet the demands of high-speed, high-resolution applications due to their high computational complexity, which heavily consumes the processor resources available on edge devices and limits their ability to support subsequent tasks. To address these challenges, this paper proposed the All-Channel Mean Spray Retinex (ACMSR) algorithm for the first time, which offers a more efficient and rapid solution for image enhancement. Furthermore, an in-situ computing ACMSR circuit is designed to eliminate the reliance on processor resources of edge devices. Compared to traditional methods, this circuit not only integrates sensing, storage, and computation in-sensor to execute the ACMSR algorithm, but also fully leverages the analog parallel computing capabilities of the memristor-crossbar-array circuit to perform architecture-level acceleration. Moreover, the proposed method achieves a processing speed of 69.3 FPS for 2K images. The circuit delivers output accuracy exceeding 98% under most types of interference.

Model Predictive Control (MPC), a receding-horizon optimal control strategy, predicts system dynamics and optimizes control actions to satisfy performance and constraint requirements, making it widely adopted in control engineering. However, contemporary computing platforms struggle to meet the real-time and energy-efficient demands of MPC’s computationally intensive matrix operations, stemming from high data movement overhead, extensive circuit resource utilization, and frequent data conversions inherent in physical system interfaces. These challenges collectively impose significant latency and power penalties, particularly critical as systems grow in complexity and scale within the big-data era. This article introduces a Zeroing Neural Network (ZNN)-based memristive neural network circuit that directly converges the MPC error function to zero in one step. Theoretical analysis and simulations validate the closed-loop circuit’s stability. For a 32-step prediction horizon, evaluations show that the control output from the proposed circuit matches the ideal digital MPC solution with 96.0% accuracy. The circuit also executes at least an order of magnitude faster and consumes less energy than traditional MPC solvers. Additionally, the circuit successfully accelerates the proposed trajectory tracking algorithm, achieving 98.0% accuracy compared with the theoretical result and 318.2× improvement in computation time compared to CPU.

Edge detection in images is the foundation of many complex tasks in computer graphics. Due to the feature loss caused by multi-layer convolution and pooling architectures, learning-based edge detection models often produce thick edges and struggle to detect the edges of small objects in images. Inspired by state space models, this paper presents an edge detection algorithm which effectively addresses the aforementioned issues. The presented algorithm obtains state space variables of the image from dual-input channels with minimal down-sampling processes and utilizes these state variables for real-time learning and memorization of image patches. To further enhance the processing speed of the algorithm, we have designed parallel computing circuits for the most computationally intensive parts of presented algorithm, significantly improving computational speed and efficiency. Simulation results demonstrate that the proposed algorithm achieves precise thin edge localization and exhibits noise suppression capabilities across various types of images. The parallel computing circuit achieves an output accuracy of over 92.13% under most interference conditions. Accelerated by this circuit, the calculation core of algorithm achieves a processing speed of 30fps on 5K images.

As a key kernel of matrix operation, lower–upper (LU) decomposition plays an important role in linear algebra and various engineering applications, such as deep learning and watermarking. Due to the complexity of large-scale matrix factorization, existing work mainly uses digital circuits and traditional computing architecture to realize LU decomposition, which inevitably faces the constraints of hardware resources and latency. Aiming at the above problem, this article first proposes the analog solver based on memristive arrays to realize LU decomposition of a nonsingular matrix in any dimension, with the advantages of high speed and parallel computing from analog circuits. The closed-loop circuit constructed therein endows it with excellent robustness and convergence characteristics during LU decomposition, and it can be performed in parallel. The simulation results indicate that the circuit designed for even 32nd-order LU matrix decomposition can achieve 95.90% accuracy. The accelerator achieved about$7\times$speed up on latency and$48.4\times$increase in TOPS performance compared to Alveo U50 FPGA, exhibiting superior performance in robustness and programming errors as well. Moreover, the proposed analog circuit serves to accelerate the embedding and extraction of digital watermarking based on LU decomposition, which enhances the invisibility of the watermark, and this application showcases the advantage of high accuracy and low energy consumption.

Quasi-cyclic moderate density parity-check McEliece (QMM) cryptosystem is designed to mitigate the security threat posed by quantum computers, and is considered to be a promising candidate for post-quantum cryptography (PQC). However, the growing requirement of data encryption pose severe challenges for QMM implementation in terms of latency and hardware overhead. In this work, we firstly propose ACIM-QMM, an analog computing-in-memory (CIM) accelerator design for QMM cryptosystem. The use of analog circuits and CIM enables the design to efficiently generate key and encrypt ciphertext while breaking the performance bottleneck constrained by digital computing paradigm in PQC. In the experiment, ACIM-QMM can work in low relative error, and it can achieve $31.4 \times \sim 288.1 \times$ speedup compared with SOTA hardware of QMM cryptosystem. Furthermore, the results indicate that ACIM-QMM can achieve a maximum of $3.12 \times$ area efficiency and $20.32 \times$ energy efficiency compared to other PQC hardware for 256-bit security.

Control systems play a crucial role in Internet of Things applications. However, in the face of increasingly complex physical environments and the sharp increase in data volume in edge computing scenarios, the transfer functions traditionally modeled through software methods tend to be offline processing. This limitation impedes the ability of Internet of Things device terminals to achieve real-time system monitoring and data analysis. In response to the challenge, this paper introduces a novel method for circuit modeling, which enables online simulation of any transfer function for the first time. Utilizing programmable memristors enables effective real-time control of system. This study validates the feasibility of the circuit modeling method by employing five engineering examples. Compared with MATLAB software modeling, the method in processing speed is at least 40 times faster and more prominent in the higher-order transfer function modeling, with a accuracy of 95.31%. Finally, this method is used to simulate an automotive cruise control system based on proportional-integral-derivative algorithm, which successfully realizes the real-time control and analysis of the dynamic behavior of the system, and also provides a new idea and technical path for the efficient and accurate dynamic management of Internet of Things systems in the future.

Riccati matrix equation (RME), a critical nonlinear matrix equation in autonomous driving and deep learning. However, memory-compute separation in traditional solving systems leads to latency and inefficiency when solving nonlinear equations, particularly under real-time requirements. Existing hardware lacks dedicated accelerators for RME, no specialized solvers quick addressing its nonlinear complexity. To address this issue, we propose a novel RME solver based on a memristive array, which leverages the parallel and fast computing advantages of analog circuits to quickly solve any order RME. Inspired by Neurodynamics for non-linear matrix equations, we first introduce an innovative Neurodynamics-based RME solving algorithm specifically designed from an analog circuit perspective. Based on this algorithm, we constructed a pioneering closed-loop analog circuit solver, overcoming bottlenecks in using circuits for such nonlinear matrix equations. Our evaluation demonstrates that the proposed solver achieves over 90% accuracy for a 128th-order parameter Riccati matrix equation. Compared to traditional digital processors, the solver offers significant energy efficiency advantages and is three orders of magnitude faster than CPU. Additionally, the solver successfully accelerates our proposed dung beetle optimizer-linear quadratic control algorithm for vehicle suspension control, achieving high precision while significantly reducing time and energy consumption compared to CPU and GPU.

The Oriented FAST and Rotated BRIEF (ORB) algorithm plays a crucial role in rapidly extracting image keypoints. However, in the domain of high-frame-rate real-time applications, the algorithm faces challenges of the speed and computational efficiency with the increase in both the size and quantity of images. To address this issue, an ORB algorithm accelerator based on a computing-in-memory (CIM) circuit is firstly proposed in this paper, which replaces the iterative calculations in traditional methods with one-step parallel analog computation. The proposed accelerator improves algorithm computational efficiency through CIM technology and enhances algorithm speed through parallel computation. Simulation demonstrate that the proposed method exhibits an average processing speed 22$\boldsymbol{\times}$faster than traditional methods and obtains more uniform corners distribution in large-scale images.

Kalman Filter (KF) algorithm, which can solve the state estimation problem of multi-variable and complex dynamical system, plays a pivotal role in a multitude of engineering scenarios. However, the traditional digital computing architecture represented by the von-Neumann architecture are currently confronted with high overhead challenges in terms of latency, energy, and area when executing KF algorithm. Aiming at the problem, we propose CIM-KF, the first Computing-in-memory (CIM) circuits for KF algorithm. CIM-KF can efficiently carry out the entire process of KF algorithm by capitalizing on the large-scale parallel computation inherent in the CIM architecture. The evaluation shows that CIM-KF has average 96.15% accuracy for 32-th order parameter matrix in KF algorithm, and can be 13.89 × ∼ 55.21 × faster than existing ASIC and FPGA implementations of KF algorithm. The results also demonstrate that CIM-KF can deliver up to 3.52 × energy efficiency improvement and 54.79 × area efficiency improvement, and reduce over 90% latency overhead, compared with the SOTA counterparts. Furthermore, we propose a novel design of ReRAM-CIM architecture, underpinned by the CIM-KF, aimed at precise and rapid calculation of the state of capacity and terminal voltage in Battery Management Systems. By evaluation, our proposed architecture boasts the estimation accuracy within 2% error for the individual battery cell of state of capacity and terminal voltage. With the strengths of the parallel computing intrinsic to CIM architecture and the speed of analog circuit, our architecture facilitates speed up to 70.6 × in accurate estimation when bench-marked against the SOTA work.

Memristive neuromorphic networks have great potential and advantage in both technology and computational protocols for artificial intelligence. Efficient hardware design of biological neuron models forms the core of research problems in neuromorphic networks. However, most of the existing research has been based on logic or integrated circuit principles, limited to replicating simple integrate-and-fire behaviors, while more complex firing characteristics have relied on the inherent properties of the devices themselves, without support from biological principles. This paper proposes a memristor-based neuron circuit system (MNCS) according to the microdynamics of neurons and complex neural cell structures. It leverages the nonlinearity and non-volatile characteristics of memristors to simulate the biological functions of various ion channels. It is designed based on the Hodgkin-Huxley (HH) model circuit, and the parameters are adjusted according to each neuronal firing mechanism. Both PSpice simulations and practical experiments have demonstrated that MNCS can replicate 24 types of repeating biological neuronal behaviors. Furthermore, the results from the Joint Inter-spike Interval(JISI) experiment indicate that as the background noise increases, MNCS exhibits pulse emission characteristics similar to those of biological neurons.

The limitations of traditional von Neumann architectures and digital computing are the bottlenecks for high-speed signal processing capabilities, not to mention the explosion of information growth. To tackle this challenge, this paper proposes an artificial neural network (ANN) equalizer based on the memristor for high-speed channel transmission at 112Gbps with 4-level pulse amplitude modulation (PAM4). To implement the PAM4 signal decision circuit based on the softmax algorithm, a comparator is used to make binary decisions for each output, and the only high-level output is further selected for the decision-making. The simulations on the PSPICE platform reveal that the number of input taps and the location of the main tap have the greatest impact on bit error rate (BER) performance. With optimal parameters, the circuit can achieve an impressive BER performance as low as 3.45E-6. To the best of our knowledge, this is the first implementation of channel equalization using memristive circuits, providing a valuable reference for analog circuit implementations of neural network equalizers.

The rapid development of artificial intelligence has brought a huge amount of data, and the traditional image processing architecture that separates sensing, storage and computation will face the problems of high power consumption and processing latency. Focusing on these problems, this paper proposed a design scheme of memristor-based optoelectronic sensing circuit, which can integrate image perception, storage, and processing into one entity. Without large-scale data transmission and conversion, the corresponding energy consumption can be avoided effectively. Firstly, an optoelectronic sensing circuit based on memristive crossbar array is proposed, which realizes the acquisition and in situ storage of image information by embedding the photoelectric converters into the memristive array. On this basis, the corresponding peripheral circuit is designed to accomplish the in situ edge feature extraction for the stored image. The extraction process is large-scale parallel computing in the analog domain, and the speed is significantly improved compared with the traditional solution. Moreover, the extraction accuracy of the circuit can reach more than 99%, and it also can withstand a certain degree of programming error and has strong robustness.

As the core operation of lattice cipher, large-scale polynomial multiplication is the biggest computational bottleneck in its realization process. How to quickly calculate polynomial multiplication under resource constraints has become an urgent problem to be solved in the hardware implementation of lattice ciphers. Therefore, an analog in-memory circuit for fast polynomial multiplication calculation is proposed. First, an in-memory computing circuit for Discrete Fourier Transform and Inverse Discrete Fourier Transform based on memristor array is designed. On this basis, a fully analog circuit that can realize polynomial multiplication in one step is designed. Compared with traditional hardware implementation, the in-memory calculation method used in this article decreases the calculation time of polynomial multiplication to the microsecond level, which greatly improves the speed of lattice cipher encryption and decryption. For the specific examples in this article, PSPICE simulation shows that the average accuracy of the calculation result is above 99.90%.

Interference alignment can overcome the shortcomings in traditional interference management. How to quickly and efficiently eliminate interference by using interference alignment is an important question. Aiming at this problem, we propose an analog in-memory circuit based on memristors for accelerating the opposite directional interference alignment algorithm, which is achieved by solving complex-valued matrix equation and multiple complex-valued matrix multiplication. The circuits can adapt to any numbers of antennas condition and adjust the memconductance to map with the channel matrix in communication systems. The evaluation shows that the circuits not only have 99% high accuracy in executing a$2\times 2$channel state but also have good robustness against some nonideal factors from wireless communication that the corresponding accuracy can exceed 95% under the 10% noise impact. Moreover, the circuits accelerate the algorithm which is three orders of magnitude faster than software.

To overcome the energy efficiency bottleneck of the von Neumann architecture and scaling limit of silicon transistors, an emerging but promising solution is neuromorphic computing, a new computing paradigm inspired by how biological neural networks handle the massive amount of information in a parallel and efficient way. Recently, there is a surge of interest in the nematode worm Caenorhabditis elegans (C. elegans), an ideal model organism to probe the mechanisms of biological neural networks. In this article, we propose a neuron model for C. elegans with leaky integrate-and-fire (LIF) dynamics and adjustable integration time. We utilize these neurons to build the C. elegans neural network according to their neural physiology, which comprises: 1) sensory modules; 2) interneuron modules; and 3) motoneuron modules. Leveraging these block designs, we develop a serpentine robot system, which mimics the locomotion behavior of C. elegans upon external stimulus. Moreover, experimental results of C. elegans neurons presented in this article reveals the robustness (1% error w.r.t. 10% random noise) and flexibility of our design in term of parameter setting. The work paves the way for future intelligent systems by mimicking the C. elegans neural system.

Complex-valued neural networks have better optimization capabilities, stronger robustness, and richer characterization capabilities compared with real-valued neural networks, which has achieved good results in the field of portrait restoration. However, there is almost no circuit implementation of complex-valued neural networks. Based on this, this article proposes an in-memory computing circuit implementation of a complex-valued Hopfield neural network (CHNN) for the first time, which provides a highly accurate and efficient processing circuit for portrait restoration. First, a new memristive array is proposed, which can realize parallel complex-valued multiplication and complex-valued vector–matrix multiplication. On the basis, a CHNN circuit that can perform large-scale recursive computations is designed. Due to the characteristics of in-memory computation, the computation speed and robustness have been improved when realizing portrait restoration. Different portrait restoration scenarios can be realized based on the programmability of the memristive array. Pspice simulation results show that the recovery speed of CHNN can reach the level of 0.1 ms, and the accuracy can reach above 97.00%. Robustness analysis shows that the circuit can tolerate a certain degree of programming error and has strong anti-noise performance.

Memristors have recently demonstrated great promise in constructing memristive neural networks with complex dynamics. This article proposes a memristive Hopfield neural network with three memristive coupling synaptic weights. The complex dynamical behaviors of the triple-memristor Hopfield neural network (TM-HNN), which have never been observed in previous Hopfield-type neural networks, include space multistructure chaotic attractors and space initial-offset coexisting behaviors. Bifurcation diagrams, Lyapunov exponents, phase portraits, Poincaré maps, and basins of attraction are used to reveal and examine the specific dynamics. Theoretical analysis and numerical simulation show that the number of space multistructure attractors can be adjusted by changing the control parameters of the memristors, and the position of space coexisting attractors can be changed by switching the initial states of the memristors. Extreme multistability emerges as a result of the TM-HNN’s unique dynamical behaviors, making it more suitable for applications based on chaos. Moreover, a digital hardware platform is developed and the space multistructure attractors as well as the space coexisting attractors are experimentally demonstrated. Finally, we design a pseudorandom number generator to explore the potential application of the proposed TM-HNN.

Matrix operations are widely used in practical engineering, but the traditional processing methods rely on the loop iterations and neural network algorithm on the software, requiring a long time to calculate. To address such problem, this paper proposes full hardware in-memory computing circuits based on programmable memristor unit array that can solve combinatorial matrix operations of any order in just one step. First, two basic circuit modules are introduced, which can respectively solve matrix multiplication and matrix equation. Further, the basic modules can be linked to solve combinatorial matrix operations with different forms. It’s worth noting that every module can parallel program the value of each memristor in the memristor unit array and complete one-step computation by hardware. Then, some matrix operations are given in the paper as examples to prove the high accuracy of proposed method, where the average accuracy rate achieves 99%. The PSPICE simulation results demonstrate that the processing speed is improved enormously according to the comparison of hardware and software. Moreover, the proposed method has broad application prospect in practical engineering, such as using designed combinational circuit to solve domain shift problem in zero-shot learning, which greatly accelerates the training process of zero-shot learning.

Training a Deep Learning (DL) model requires proprietary data and computing-intensive resources. To recoup their training costs, a model provider can monetize DL models through Machine Learning as a Service (MLaaS). Generally, the model is deployed at the cloud, while providing a publicly accessible Application Programming Interface (API) for paid queries to obtain benefits. However, model stealing attacks have posed security threats to this model monetizing scheme as they steal the model without paying for future extensive queries. Specifically, an adversary queries a targeted model to obtain input-output pairs and thus infer the model’s internal working mechanism by reverse-engineering a substitute model, which has deprived model owner’s business advantage and leaked the privacy of the model. In this work, we observe that the confidence vector or the top-1 confidence returned from the model under attack (MUA) varies in a relative large degree given different queried inputs. Therefore, rich internal information of the MUA is leaked to the attacker that facilities her reconstruction of a substitute model. We thus propose to leverage adversarial confidence perturbation to hide such varied confidence distribution given different queries, consequentially against model stealing attacks (dubbed as APMSA). In other words, the confidence vectors returned now is similar for queries from a specific category, considerably reducing information leakage of the MUA. To achieve this objective, through automated optimization, we constructively add delicate noise into per input query to make its confidence close to the decision boundary of the MUA. Generally, this process is achieved in a similar means of crafting adversarial examples but with a distinction that the hard label is preserved to be the same as the queried input. This retains the inference utility (i.e., without sacrificing the inference accuracy) for normal users but bounded the leaked confidence information to the attacker in a small constrained area (i.e., close to decision boundary). The later renders greatly deteriorated accuracy of the attacker’s substitute model. As the APMSA serves as a plug-in front-end and requires no change to the MUA, it is thus generic and easy to deploy. The high efficacy of APMSA is validated through experiments on datasets of CIFAR10 and GTSRB. Given a MUA model of ResNet-18 on the CIFAR10, our defense can degrade the accuracy of the stolen model by up to 15% (rendering the stolen model useless to a large extent) with 0% accuracy drop for normal user’s hard-label inference request.

Discrete Hartley transform is a core component of digital signal processing because of its advantages of fast computing speed and less power consumption. Traditional FPGA-based implementation methods have the disadvantage of high latency, which cannot meet the needs of energy-efficient computing in the Internet of Things era. Therefore, A programmable analog memory computing circuit is proposed to accelerate FHT and IFHT calculations for large-scale one-step matrix computation. By adjusting the weight of memristor, different scales of FHT calculation can be achieved. PSPICE simulation results show that the average accuracy of the proposed circuit can reach 99.9%, and the speed can also reach the level of 0.1 μs. The robustness analysis shows that the circuit can tolerate a certain degree of programming error and resistance tolerance. The designed analog circuit is applied to image compression processing, and the image compression accuracy can reach 99.9%.

Equality-constrained quadratic programming (QP) has been one of the most basic and typical problems in the Internet of Things domain. In big data scenarios, how to quickly and accurately solve the problem in hardware has not been realized. Therefore, in this article, a memristive recurrent neural circuit that can parallel solve the QP problem in real time is proposed. First, a new memristive synaptic array is designed that can simultaneously implement parallel reading and writing. On the basis of this structure, a new neural network circuit based on memristor is designed that can perform large-scale recursive operations by parallel methods. This circuit can solve the equality-constrained QP problem in different situations by using such real-time programmable memristor arrays processing in memory. The PSpice simulation results show that the problem can be solved with 99.8% precision. Based on practical verification, the neural circuit experiment on PCB is presented with 97.34% precision. Moreover, the circuit has good robustness under the interference of weight value. And, it has an advantage in processing time compared with FPGA.

With the development of intelligent transportation system (ITS), the vital technology of ITS, short-term traffic forecasting, gains increasing attention. However, the existing prediction models ignore the impact of urban functional zones (FZs) on traffic data, resulting in inaccurate extractions of dynamic spatial relationships from network. Furthermore, how to calculate the influence of external factors, such as weather and holidays on traffic is an unsolved problem. This article proposes a spatio-temporal hierarchical mapping and interactive attention network (HMIAN), which extracts the spatial features from traffic network by constructing FZs, and designs an effective external factors fusion method. HMIAN uses the hierarchical mapping structure to aggregate the roads into FZs, calculate the interaction between FZs and feed this information back to the spatial features. And the interactive attention mechanism is utilized to fuse the traffic data with external factors effectively, and extracts temporal features. In addition, some experiments were carried out on three real traffic data sets. First, experiment results show the better prediction performance of the proposed model compared with other existing methods in a complex traffic network. Second, the longitudinal comparison experiment verifies that the hierarchical mapping structure is effective in extracting spatial features in a complex road network. Finally, the influence of different external factors and fusion methods on traffic prediction are compared, which provides a consult for subsequent research on the influence of external factors.

The analog circuit design of the memristive neural network (MNN), which can automatically perform the online learning algorithm, is an open question. In this article, a memristive self-learning neuron circuit for implementing the online least mean square (LMS) algorithm is designed. Extending on the designed neuron circuit, the circuit implementation of the monolayer and multilayer neural network is proposed. The proposed neural network can automatically converge the output to the set target according to the input. The application-level validations of the circuits are done using pattern recognition and license plate detection. The performances of the designed MNN circuits and the effect of memristive variation are analyzed through PSPICE simulations. The learning accuracy of the proposed circuit for license plate detection can reach 93%. Circuit simulation results reveal that the proposed MNN circuits can accelerate the training speed and have the tolerance to the variations of the memristor.

Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT) are core components in the field of signal processing. However, in the existing research, there is no fully analog circuit that can realize the one-step calculation of FFT. Therefore, in this paper, an analog circuit that can calculate FFT and its inverse transform IFFT in one-step is proposed. First, a circuit that can realize complex number operations is designed. On the basis of this structure, a fully analog circuit that can realize fast and efficient computing of FFT and IFFT in one-step is proposed. In addition, different coefficient matching can be obtained to achieve arbitrary points of FFT and IFFT by adjusting the resistance value of the memristor, which has good programmability. Specific examples are given in the paper to evaluate the proposed method. The PSPICE simulation results show that the average accuracy is above 99.98%. More importantly, the calculation speed has been greatly improved compared with MATLAB simulation. Finally, the proposed circuit can be used to quickly solve convolution operation, and the average accuracy can reach 99.95%.

A large number of studies have shown that astrocytes can be combined with the presynaptic terminals and postsynaptic spines of neurons to constitute a triple synapse via an endocannabinoid retrograde messenger to achieve a self-repair ability in the human brain. Inspired by the biological self-repair mechanism of astrocytes, this work proposes a self-repairing neuron network circuit that utilizes a memristor to simulate changes in neurotransmitters when a set threshold is reached. The proposed circuit simulates an astrocyte-neuron network and comprises the following: 1) a single-astrocyte-neuron circuit module; 2) an astrocyte-neuron network circuit; 3) a module to detect malfunctions; and 4) a neuron PR (release probability of synaptic transmission) enhancement module. When faults occur in a synapse, the neuron module becomes silent or near silent because of the low PR of the synapses. The circuit can detect faults automatically. The damaged neuron can be repaired by enhancing the PR of other healthy neurons, analogous to the biological repair mechanism of astrocytes. This mechanism helps to repair the damaged circuit. A simulation of the circuit revealed the following: 1) as the number of neurons in the circuit increases, the self-repair ability strengthens and 2) as the number of damaged neurons in the astrocyte-neuron network increases, the self-repair ability weakens, and there is a significant degradation in the performance of the circuit. The self-repairing circuit was used for a robot, and it effectively improved the robots' performance and reliability.

In this article, we propose a novel chaotic neuron circuit with memristive neural synapses, construct an architecture of memristive chaotic neural network (MCNN) and implement associative memory application of bipolar images. The proposed neuron circuit mainly consists of synapse module and neuron module with chaotic dynamics characteristics. The synapse module is composed of memristors which represent synaptic weights. The neuron module employs voltage feedback operational amplifiers to accomplish integral operation and output function. MCNN utilizes a memristor crossbar array to perform matrix operations and can process the information in parallel. In addition, the proposed circuit of MCNN can accomplish continuous recursive operations and meet different applications due to the programmability of the memristor. The ex-situ method is utilized to train the memristor crossbar array. Furthermore, the associative memory applications of bipolar images are carried out based on the constructed circuits of MCNN with three and nine neurons. The simulation results in PSPICE software testify the functions of the MCNN circuit.

Inhomogeneous linear ordinary differential equations (ODEs) and systems of ODEs can be solved in a variety of ways. However, hardware circuits that can perform the efficient analog computation to solve them are rarely in the literature. To address such problems, this paper proposes a general method of using a memristor-capacitor (M-C) circuit to solve inhomogeneous linear ODEs and systems of ODEs of any order in initial value problems. The M-C circuit can match the coefficients of the equations sought by adjusting the memristor resistance value according to the coefficient formula proposed in the paper, which has higher programmability. Then, some ODEs and systems of ODEs are given in the paper as examples to evaluate the proposed method. According to the comparison results based on MATLAB software simulation and the simulation based on OrCAD software, the designed M-C circuit has an effective improvement in speed and the accuracy exceeds 99.95% in software simulation. Based on practical verification, this paper gives the actual M-C circuit experiment based on PCB. Moreover, the proposed method can be used to quickly solve the object motion state in the spring mass damping system in actual engineering, and the accuracy can reach 99.98%.

Nowadays, research, modeling, simulation and realization of brain-like systems to reproduce brain behaviors have become urgent requirements. In this paper, neural bursting and synchronization are imitated by modeling two neural network models based on the Hopfield neural network (HNN). The first neural network model consists of four neurons, which correspond to realizing neural bursting firings. Theoretical analysis and numerical simulation show that the simple neural network can generate abundant bursting dynamics including multiple periodic bursting firings with different spikes per burst, multiple coexisting bursting firings, as well as multiple chaotic bursting firings with different amplitudes. The second neural network model simulates neural synchronization using a coupling neural network composed of two above small neural networks. The synchronization dynamics of the coupling neural network is theoretically proved based on the Lyapunov stability theory. Extensive simulation results show that the coupling neural network can produce different types of synchronous behaviors dependent on synaptic coupling strength, such as anti-phase bursting synchronization, anti-phase spiking synchronization, and complete bursting synchronization. Finally, two neural network circuits are designed and implemented to show the effectiveness and potential of the constructed neural networks.

Biological long short-term memory (B-LSTM) can effectively help human process all kinds of received information. In this work, a memristive B-LSTM circuit which mimics a conversion from short-term memory to long-term memory is proposed. That is, the stronger the signal, the more profound the memory and the higher the output. On this basis, an image binarization circuit using adaptive row threshold algorithm is proposed. It can make the image remain a deep impression on the strong pixel information and effectively filter the relatively weak pixel information. In combination with the function of image binarization, a memristive circuit for eyes state detection is proposed by adding corresponding horizontal projection calculation, subtraction calculation and judgement open or closed eyes modules. The proposed circuit can detect whether there is a blink between two adjacent facial images, which uses the characteristics of memristor to detect the difference of horizontal projection between two images. Due to the use of memristor, the proposed circuit can realize in-memory computing, which fundamentally avoids the problem of storage wall and shorten the execution time. Finally, an expectation application in fatigue driving based on the proposed method is demonstrated, which indicates the practicability of the circuit design in this work.

In this article, we design a memristive competitive neural network circuit based on the winner-take-all (WTA) mechanism and the online Hebbian learning rule. Each synapse of the network contains two memristors whose terminals of signal inputs are opposite. However, only one memristor participates in the calculation each time, and that one is determined by the original input signal. The competitive neural network circuit includes two parts: forward calculation and weight update. In this article, the forward calculation part of the circuit is designed based on the WTA mechanism. The combination of the leaky-integrate-and-fire (LIF) model and pMOS realizes the lateral inhibition of neurons. The design of the weight updating part is based on Hebbian learning rules. In each cycle, only synaptic memristors connected to the winner output neuron in forward calculation can be adjusted. The voltage used for synaptic memristor adjustment comes from the membrane voltage of the winner output neuron. The whole neural network circuit does not need the participation of a central processing unit (CPU) or a field-programmable gate array (FPGA) and really realizes parallel calculation, the saving of area, power consumption, and a certain extent computing-in-memory. Based on the circuit designed in PSPICE, we simulated the classification of$5\times3$pixel pictures. The changing trend of weights in the training phase and the high recognition accuracy in the recognition phase prove that the network can learn and recognize different patterns. The competitive neural network can be applied to the neuromorphic system of visual pattern recognition.

In order to overcome the essential difficulties in conventional nonlinear control with iteratively adjusting multiple parameters, a novel method for designing multidirection multibutterfly chaotic attractors (MDMBCAs) without reconstructing nonlinear functions is proposed. By using a unified pulse control in a modified Lorenz system, a family of complete multibutterfly attractors can be produced, including 1-D, 2-D, and 3-D multibutterfly attractors. Theoretical analysis and numerical simulations show that arbitrary MDMBCA all can be generated by conducting the pulse-control in corresponding state variable direction (1-D), plane (2-D), or space (3-D). Meanwhile, the number of butterfly attractors can be controlled with the number of pulsed excitation. Furthermore, we design a module-based unified realization circuit and arbitrary MDMBCA can be obtained by selecting corresponding pulsed-excitation. Our theoretical analysis, MATLAB simulations and circuit experiments together show the effectiveness and universality of the proposed methodology. It should be especially pointed out that the proposed method is a universal scheme and can be applied in the arbitrary double-wing chaotic system.

In this paper, a novel nonlinear function shift method for generating multiscroll attractors is proposed, and a memristor-based control circuit is used to realize the shift controller. Three types of shift modes, namely, horizontal shift, vertical shift, and combined shift, are added in a Jerk system. The dynamic behavior is analyzed through equilibria distribution, bifurcation diagram, Lyapunov exponent spectrum, and phase portraits. Research shows that various equilibria distributions and bifurcation phenomena can be obtained by adding different shifts, thereby producing diverse attractors including periodic orbits, single-scroll, double-scroll, and multiscroll attractors. Furthermore, symmetrical and asymmetrical attractors that are unusual dynamic behaviors can also be found. The circuit construction based on CMOS technology is given, and a memristor-based control circuit is designed to implement the proposed shift method. Different multiscroll attractors can be obtained by regulating the applied control signals instead of redesigning the nonlinear circuit, which simplifies the circuit design of multiscroll system. Our theoretical analysis, numerical simulations, and PSpice simulations together demonstrate the simpleness and effectiveness of the proposed methodology.