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Varun Gohil

dblp:227/8088 · DBLP profile ↗
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5ranked-venue papers
1as first author
3since 2021 · last 2025
0000-0003-4929-9237ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author · 2 since 2021Computer networks · 1Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Cloud and datacenter computing · 44% Hardware accelerators and domain-specific architectures · 20% Performance modeling and evaluation · 18%
Artificial intelligence
1 paper
Trustworthy machine learning · 100%
Databases, data mining, and information retrieval
1 paper
Machine learning and data management · 100%

Topics — the 9 heaviest of 12, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Machine learning › Trustworthy machine learning › uncertainty estimation
confidence estimation
0.912025
The Importance of Generalizability in Machine Learning for Systems · HPCA 2025
Machine learning › Trustworthy machine learning › robustness
out-of-distribution detection
0.912025
The Importance of Generalizability in Machine Learning for Systems · HPCA 2025
Cloud and datacenter computing
resource management
0.912025
The Importance of Generalizability in Machine Learning for Systems · HPCA 2025
Hardware accelerators and domain-specific architectures › domain-specific accelerator
compression accelerator
0.812024
Sabre: Hardware-Accelerated Snapshot Compression for Serverless MicroVMs · OSDI 2024
Cloud and datacenter computing
serverless computing
0.812024
Sabre: Hardware-Accelerated Snapshot Compression for Serverless MicroVMs · OSDI 2024
Memory systems
non-volatile memory
0.312018
META: Memory Exploration Tool for Android Devices · MobiCom 2018
Performance modeling and evaluation
simulation
0.312018
META: Memory Exploration Tool for Android Devices · MobiCom 2018
Performance modeling and evaluation › simulation › discrete-event simulation
trace-driven simulation
0.312018
META: Memory Exploration Tool for Android Devices · MobiCom 2018
Machine learning and data management
machine learning for systems
0.312025
The Importance of Generalizability in Machine Learning for Systems · HPCA 2025

Methods — techniques the papers use, named apart from their topics

out-of-distribution detection · 2.6bayesian model · 2.6hardware acceleration · 0.8cache simulation · 0.3android emulator · 0.3
YearPublicationVenuePosition
2025 The Importance of Generalizability in Machine Learning for Systems
abstract
Using machine learning (ML) to tackle computer systems tasks is gaining popularity. One of the shortcomings of such ML-based approaches is the inability of models to generalize to out-ofdistribution data i.e., data whose distribution is different than the training dataset. We showcase that this issue exists in cloud environments by analyzing various ML models used to improve resource balance in Google’s fleet. We discuss the trade-offs associated with different techniques used to detect out-of-distribution data. Finally, we propose and demonstrate the efficacy of using Bayesian models to detect the model’s confidence in its output when used to improve cloud server resource balance.
Varun Gohil, Sundar Dev, Gaurang Upasani, David Lo 0003, Parthasarathy Ranganathan, Christina Delimitrou
HPCA1
2024 The Sunk Carbon Fallacy: Rethinking Carbon Footprint Metrics for Effective Carbon-Aware Scheduling
abstract
The rapid increase in computing demand and corresponding energy consumption have focused attention on computing's impact on the climate and sustainability. Prior work proposes metrics that quantify computing's carbon footprint across several lifecycle phases, including its supply chain, operation, and end-of-life. Industry uses these metrics to optimize the carbon footprint of manufacturing hardware and running computing applications. Unfortunately, prior work on optimizing datacenters' carbon footprint often succumbs to the sunk cost fallacy by considering embodied carbon emissions (a sunk cost) when making operational decisions (i.e., job scheduling and placement), which leads to operational decisions that do not always reduce the total carbon footprint.
Noman Bashir, Varun Gohil, Anagha Belavadi Subramanya, Mohammad Shahrad, David Irwin 0001, Elsa Olivetti, Christina Delimitrou
SoCC2
2024 Sabre: Hardware-Accelerated Snapshot Compression for Serverless MicroVMs
Nikita Lazarev, Varun Gohil, James Tsai, Andy Anderson, Bhushan Chitlur, Zhiru Zhang, Christina Delimitrou
OSDI2
2020 Prefetching in Hybrid Main Memory Systems
Subisha V, Varun Gohil, Nisarg Ujjainkar, Manu Awasthi
HotStorage2
2018 META: Memory Exploration Tool for Android Devices
abstract
Handheld devices are becoming increasingly common in today's world. With every passing year, the diversity of applications (apps) being supported by mobile platforms is growing manyfold. In addition, Android, the most popular handheld OS in the market is releasing a new version every year, with a newer and richer set of APIs, enabling the next generation of feature-rich applications. To support these apps, hardware requirements of these devices are increasing rapidly. Mobile SoCs need a larger number of faster cores, better GPUs and above all, higher DRAM capacities to do justice to user experience. To augment capacity requirements, non-volatile memories (NVMs) have been proposed as a potential addition to LPDDR variants, which have been the mainstay of mobile SoCs. However, few tools exist to carry out architectural design space exploration of main memory hierarchies featuring NVMs for newer Android and app versions. In this paper, we present META, a trace based tool for facilitating the exploration of memory hierarchies in mobile devices. META uses an enhanced version of Android emulator for generating raw instruction traces. These traces are then fed into a cache hierarchy and memory simulation modules to carry out design space exploration for a wide variety of apps and memory technologies.
Nisarg Parikh, Varun Gohil, Manu Awasthi
MobiCom2