Abhijitt Dhavlle

dblp:229/2750 · DBLP profile ↗
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9ranked-venue papers
5as first author
7since 2021 · last 2023
0000-0003-4789-6484ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 9 · 5 first-author · 7 since 2021Software engineering, systems software and programming languages · 2 · 2 first-author · 2 since 2021
YearPublicationVenuePosition
2023 Defense Against On-Chip Trojans Enabling Traffic Analysis Attacks Based on Machine Learning and Data Augmentation
abstract
Modern computing systems involve huge data exchange across various sections of the processing system. To facilitate this, network-on-chip (NoC) serves as a crucial infrastructure that connects the processing cores to memory, peripherals, etc. The system could be put at great risk should the NoC system become compromised. The NoCs are used in multi/many-core processors; this domain is experiencing increased threats because of hardware Trojan (HT) embedded in the multicore processing systems due to the presence of third-party entities in the system-on-chip (SoC) design pipeline. Protecting user and system level privacy becomes important in such multi core systems to enable trust. By embedding an HT in an NoC, the adversary can snoop on important insights regarding the applications executing on the system or the user profile information. An attack of such calibre can compromise privacy, thereby enabling more advanced attack on the entire system. This work demonstrates the capability of a traffic analysis attack when a few HTs are embedded in the NoC switches of a multi/many-core processor. The attack is capable of exposing sensitive information to an external malicious attacker who can then analyze the payload data with sophisticated machine learning (ML) techniques to infer the applications executing on the system. We also evaluate the performance of a generative adversarial network (GAN) strengthened attacker model that offers more robustness for data paucity scenarios. We propose a simulated annealing-based randomized routing algorithm based defense for NoCs, thus thwarting the attack. The results demonstrate that the proposed randomized routing algorithm could reduce the accuracy of identifying user profiles by the attacker from$>$98% to < 15% in multi/many-core systems.
Abhijitt Dhavlle, M. Meraj Ahmed, Naseef Mansoor, Kanad Basu, Amlan Ganguly, Sai Manoj Pudukotai Dinakarrao
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2022 CR-Spectre: Defense-Aware ROP Injected Code-Reuse Based Dynamic Spectre
abstract
Side-channel attacks have been a constant threat to computing systems. In recent times, vulnerabilities in the architecture were discovered and exploited to mount and execute a state-of-the-art attack such as Spectre. The Spectre attack exploits a vulnerability in the Intel-based processors to leak confidential data through the covert channel. There exist some defenses to mitigate the Spectre attack. Among multiple defenses, hardware-assisted attack/intrusion detection (HID) systems have received overwhelming response due to its low overhead and efficient attack detection. The HID systems deploy machine learning (ML) classifiers to perform anomaly detection to determine whether the system is under attack. For this purpose, a performance monitoring tool profiles the applications to record hardware performance counters (HPC), utilized for anomaly detection. Previous HID systems assume that the Spectre is executed as a standalone application. In contrast, we propose an attack that dynamically generates variations in the injected code to evade detection. The attack is injected into a benign application. In this manner, the attack conceals itself as a benign application and gen-erates perturbations to avoid detection. For the attack injection, we exploit a return-oriented programming (ROP)-based code-injection technique that reuses the code, called gadgets, present in the exploited victim's (host) memory to execute the attack, which, in our case, is the CR-Spectre attack to steal sensitive data from a target victim (target) application. Our work focuses on proposing a dynamic attack that can evade HID detection by injecting perturbations, and its dynamically generated variations thereof, under the cloak of a benign application. We evaluate the proposed attack on the MiBench suite as the host. From our experiments, the HID performance degrades from 90% to 16%, indicating our Spectre-CR attack avoids detection successfully.
Abhijitt Dhavlle, Setareh Rafatirad, Houman Homayoun, Sai Manoj Pudukotai Dinakarrao
DATE1
2022 Iron-Dome: Securing IoT Networked Systems at Runtime by Network and Device Characteristics to Confine Malware Epidemics
abstract
The rapid growth of IoT networks presents an enlarged "attack space" for the adversary and poses significant security risks on a large scale. A single device in a network that is compromised under the influence of a malware attack, has the potential to spread malware across the network. This leads to a plethora of attacks, including DoS and ceasing the network functionality. Given the scale of IoT networks and the connectivity among the devices, mere detection and quarantining of malware in IoT networks does not limit the propagation of malware in IoT networks. This work proposes an integrated defense, termed as "IRON-DOME", comprising of (1) an on-device application analyzer: Image-based Malware detector that utilizes grayscale images of executables, (2) Device dynamic behavior analysis: Reliable extraction and dynamic analysis of malware Hardware Performance Counter (HPC) values; and (3) Device communication trait analyzer: Uses network packet data analysis to confine and propagate malware in the IoT network. The proposed solution yields: (1) a runtime malware detection accuracy of 93% within 19 ns, (2) is resource and power efficient; it consumes 30% fewer resources and 40% less power than state-of-the art defense techniques.
Sanket Shukla, Abhijitt Dhavlle, Sai Manoj Pudukotai Dinakarrao, Houman Homayoun, Setareh Rafatirad
ICCD2
2022 Imitating Functional Operations for Mitigating Side-Channel Leakage
abstract
Inspired by the idiom, “Mitigation (prevention) is better than cure!”, this work presents a random yet cognitive side-channel mitigation technique that is independent of underlying architecture and/or operating system. Unlike malware and other cyber-attacks, side-channel attacks (SCAs) exploit the architectural and design vulnerabilities and obtain sensitive information through the side channels. In contrast to the existing randomization-based side-channel defenses, we introduce a cognitive perturbation-based defense, Covert-Enigma, where the introduced perturbations look legit, but lead to an incorrect observation when interpreted by the attacker. To achieve this, the perturbations are injected at appropriate time instances to introduce additional operations, thereby misleading the attacker making the extracted data futile. To further make the attack more intricate for the attacker, proposed Covert-Enigma offers two modes of operation, chosen by the user, to determine the kind of induced cognitive perturbations—arbitraryandcyclicmodes. Arbitrary mode selects a group of key bits and flips them during every execution of the victim. Cyclic mode exhibits similar behavior, except it selects a new set of bits to flip after “$N$” cycles as chosen by the user. The cognitive perturbations are introduced in the form of a wrapper application to the victim, thus imposing no requirements on architectural level modifications nor soft updates/edits to the operating system. We report rigorous evaluation of the proposed Covert-Enigma protecting RSA cryptosystem attacked by Flush+Reload crypto SCA along with the bit(s) recovered after observing RSA under attack. Compared to traditional randomization-based defenses, proposed cognitive Covert-Enigma leads to 50% less overhead.
Abhijitt Dhavlle, Setareh Rafatirad, Khaled N. Khasawneh, Houman Homayoun, Sai Manoj Pudukotai Dinakarrao
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2021 HMD-Hardener: Adversarially Robust and Efficient Hardware-Assisted Runtime Malware Detection
abstract
To overcome the performance overheads incurred by the traditional software-based malware detection techniques, machine learning (ML) based Hardware-assisted Malware Detection (HMD) has emerged as a panacea to detect malicious applications and provide security. HMD primarily relies on the generated low-level microarchitectural events captured through Hardware Performance Counters (HPCs). This work proposes an adversarial attack on the HMD systems to tamper the security by introducing perturbations in performance counter traces with an adversarial sample generator application. To craft the attack, we first deploy an adversarial sample predictor to predict the adversarial HPC pattern for a given application to be misclassified by the deployed ML classifier in the HMD. Further, as the attacker has no direct access to manipulate the HPCs generated during runtime, based on the adversarial sample predictor's output, devise an adversarial sample generator wrapped around the victim application to produce HPC patterns similar to the adversarial predictor's estimated trace. With the proposed attack, malware detection accuracy is reduced to 18.1% from 82%. To render the HMD robust to such attacks, we further propose adversarially training the HMD to demonstrate that hardening can render HMD resilient against attacks; the detection accuracy post hardening raises to 81.2%.
Abhijitt Dhavlle, Sanket Shukla, Setareh Rafatirad, Houman Homayoun, Sai Manoj Pudukotai Dinakarrao
DATE1
2021 What Can a Remote Access Hardware Trojan do to a Network-on-Chip?
abstract
Interconnection networks such as Network-on-Chips (NoCs) for multi/many-core processors are critical infrastructure of the system as they enable data communication among the processing cores, caches, memory, and other peripherals. Given the criticality of the interconnects, the system can be severely subverted if the interconnection is compromised. The threat of Hardware Trojans (HTs) penetrating complex hardware systems such as multi/many-core processors are increasing due to the increasing presence of third party players in a System-on-chip (SoC) design. Even by deploying naïve HTs, an adversary can exploit the NoC backbone of the processor and get access to communication patterns in the system. In this paper, we discuss that one or more HTs embedded in the NoC of a multi/many-core processor is capable of leaking sensitive information regarding traffic patterns to an external malicious attacker; who, in turn, can analyze the HT payload data with advanced algorithms such as machine learning to infer the applications running on the processor or reverse engineer architectural Intellectual Property (IP) of the system. Here, we entertain the idea of using routing obfuscation to achieve a desired trade-off between defense against HTs and performance penalties. We also discuss the possibility of making this trade-off a tunable design parameter that can be adjusted at run-time based on external threat perception.
M. Meraj Ahmed, Abhijitt Dhavlle, Naseef Mansoor, Sai Manoj Pudukotai Dinakarrao, Kanad Basu, Amlan Ganguly
ISCAS2
2021 Design of Hardware Trojans and its Impact on CPS Systems: A Comprehensive Survey
abstract
The ever-increasing demand for sophisticated cyber- physical systems (CPS), combined with the fabless model, led to vulnerability exploits in the IC supply chain, especially the insertion of hardware Trojans (HTs). The HTs are malicious modifications made to an authentic design to disrupt the functioning of the integrated circuits (ICs). In this work, we present a survey of the state-of-the-art HT designs focusing on the Trojan design, the risk level in the supply chain, and the targeted platform, followed by a discussion based on our observations. We categorize the HT designs based on the targeted platforms such as ML accelerators, IoT devices, FPGAs, ASICs, memory devices, CPU, and Cryptographic cores.
Abhijitt Dhavlle, Rakibul Hassan, Manideep Mittapalli, Sai Manoj Pudukotai Dinakarrao
ISCAS1
2019 Adversarial Attack on Microarchitectural Events based Malware Detectors
abstract
To overcome the performance overheads incurred by the traditional software-based malware detection techniques, Hardware-assisted Malware Detection (HMD) using machine learning (ML) classifiers has emerged as a panacea to detect malicious applications and secure the systems. To classify benign and malicious applications, HMD primarily relies on the generated low-level microarchitectural events captured through Hardware Performance Counters (HPCs). This work creates an adversarial attack on the HMD systems to tamper the security by introducing the perturbations in the HPC traces with the aid of an adversarial sample generator application. To craft the attack, we first deploy an adversarial sample predictor to predict the adversarial HPC pattern for a given application to be misclassified by the deployed ML classifier in the HMD. Further, as the attacker has no direct access to manipulate the HPCs generated during runtime, based on the output of the adversarial sample predictor, we devise an adversarial sample generator wrapped around a normal application to produce HPC patterns similar to the adversarial predictor HPC trace. As the crafted adversarial sample generator application does not have any malicious operations, it is not detectable with traditional signature-based malware detection solutions. With the proposed attack, malware detection accuracy has been reduced to 18.04% from 82.76%.
Sai Manoj Pudukotai Dinakarrao, Sairaj Amberkar, Sahil Bhat, Abhijitt Dhavlle, Hossein Sayadi, Avesta Sasan, Houman Homayoun, Setareh Rafatirad
DAC4
2018 Advances and throwbacks in hardware-assisted security: special session
Ferdinand Brasser, Lucas Davi, Abhijitt Dhavlle, Tommaso Frassetto, Sai Manoj Pudukotai Dinakarrao, Setareh Rafatirad, Ahmad-Reza Sadeghi, Avesta Sasan, Hossein Sayadi, Shaza Zeitouni, Houman Homayoun
CASES3