Demo Data from VLDB 2026 / reviewers in the wild / expert
Stephen I. Roberts
dblp:229/4260
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 2019
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Energy-efficient computing · 87% Performance modeling and evaluation · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Energy-efficient computing › power-performance modeling
energy-delay modeling |
0.4 | 1 | 2019 | The Power-optimised Software Envelope · ACM Trans. Archit. Code Optim. 2019 |
Energy-efficient computing › low-power design
power optimization |
0.4 | 1 | 2019 | The Power-optimised Software Envelope · ACM Trans. Archit. Code Optim. 2019 |
Performance modeling and evaluation › benchmarking › benchmark suite analysis
benchmark characterization |
0.1 | 1 | 2019 | The Power-optimised Software Envelope · ACM Trans. Archit. Code Optim. 2019 |
Methods — techniques the papers use, named apart from their topics
meta-heuristic · 0.4energy-delay product · 0.4POSE model · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2019 | The Power-optimised Software EnvelopeabstractAdvances in processor design have delivered performance improvements for decades. As physical limits are reached, refinements to the same basic technologies are beginning to yield diminishing returns. Unsustainable increases in energy consumption are forcing hardware manufacturers to prioritise energy efficiency in their designs. Research suggests that software modifications may be needed to exploit the resulting improvements in current and future hardware. New tools are required to capitalise on this new class of optimisation. In this article, we present the Power Optimised Software Envelope (POSE) model, which allows developers to assess the potential benefits of power optimisation for their applications. The POSE model is metric agnostic and in this article, we provide derivations using the established Energy-Delay Product metric and the novel Energy-Delay Sum and Energy-Delay Distance metrics that we believe are more appropriate for energy-aware optimisation efforts. We demonstrate POSE on three platforms by studying the optimisation characteristics of applications from the Mantevo benchmark suite. Our results show that the Pathfinder application has very little scope for power optimisation while TeaLeaf has the most, with all other applications in the benchmark suite falling between the two. Finally, we extend our POSE model with a formulation known as System Summary POSE—a meta-heuristic that allows developers to assess the scope a system has for energy-aware software optimisation independent of the code being run. Stephen I. Roberts, Steven A. Wright 0001, Suhaib A. Fahmy, Stephen A. Jarvis |
ACM Trans. Archit. Code Optim. | 1 |