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Tugba Torun

dblp:229/9413 · DBLP profile ↗
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3ranked-venue papers
0as first author
2since 2021 · last 2023
0000-0001-6790-7094ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
High-performance computing · 74% Electronic design automation · 14% Performance modeling and evaluation · 8%

Topics — the 6 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
High-performance computing › sparse linear algebra
matrix ordering
0.712023
Bringing Order to Sparsity: A Sparse Matrix Reordering Study on Multicore CPUs · SC 2023
High-performance computing › sparse linear algebra
sparse matrix computation
0.712023
Bringing Order to Sparsity: A Sparse Matrix Reordering Study on Multicore CPUs · SC 2023
Electronic design automation › physical design › circuit partitioning
hypergraph partitioning
0.312018
Improving Medium-Grain Partitioning for Scalable Sparse Tensor Decomposition · IEEE Trans. Parallel Distributed Syst. 2018
High-performance computing › tensor computation
tensor decomposition
0.312018
Improving Medium-Grain Partitioning for Scalable Sparse Tensor Decomposition · IEEE Trans. Parallel Distributed Syst. 2018
Parallel and multicore computing › data distribution
cartesian partitioning
0.112018
Improving Medium-Grain Partitioning for Scalable Sparse Tensor Decomposition · IEEE Trans. Parallel Distributed Syst. 2018
High-performance computing
distributed memory systems
0.112018
Improving Medium-Grain Partitioning for Scalable Sparse Tensor Decomposition · IEEE Trans. Parallel Distributed Syst. 2018

Methods — techniques the papers use, named apart from their topics

matrix reordering algorithms · 0.7graph partitioning · 0.7hypergraph partitioning · 0.3
YearPublicationVenuePosition
2023 Bringing Order to Sparsity: A Sparse Matrix Reordering Study on Multicore CPUs
abstract
Many real-world computations involve sparse data structures in the form of sparse matrices. A common strategy for optimizing sparse matrix operations is to reorder a matrix to improve data locality. However, it's not always clear whether reordering will provide benefits over the unordered matrix, as its effectiveness depends on several factors, such as structural features of the matrix, the reordering algorithm and the hardware that is used. This paper aims to establish the relationship between matrix reordering algorithms and the performance of sparse matrix operations. We thoroughly evaluate six different matrix reordering algorithms on 490 matrices across eight multicore architectures, focusing on the commonly used sparse matrix-vector multiplication (SpMV) kernel. We find that reordering based on graph partitioning provides better SpMV performance than the alternatives for a large majority of matrices, and that the resulting performance is explained through a combination of data locality and load balancing concerns.
James D. Trotter, Sinan Ekmekçibasi, Johannes Langguth, Tugba Torun, Emre Düzakin, Aleksandar Ilic, Didem Unat
SC4
2022 Mixed and Multi-Precision SpMV for GPUs with Row-wise Precision Selection
abstract
Sparse Matrix-Vector Multiplication (SpMV) is one of the key memory-bound kernels commonly used in industrial and scientific applications. To improve its data movement and benefit from higher compute rates, there are several efforts to utilize mixed precision on SpMV. Most of the prior-art focus on performing the entire SpMV in single-precision within a bigger context of an iterative solver (e.g., CG, GMRES). In this work, we are interested in a more fine-grained mixed-precision SpMV, where the level of precision is decided for each element in the matrix to be used in a single operation. We extend an existing entry-wise precision based approach by deciding precisions per row, motivated by the granularity of parallelism on a GPU where groups of threads process rows in CSR-based matrices. We propose mixed-precision CSR storage methods with row permutations and describe their greater efficiency and load-balancing compared to the existing method. We also consider a multi-precision case where single and double precision copies of the matrix are stored priorly and further extend our mixed-precision SpMV approach to comply with it. As such, we leverage a mixed-precision SpMV to obtain a multi-precision Jacobi method which is faster than yet almost as accurate as double-precision Jacobi implementation, and further evaluate a multi-precision Cardiac modeling algorithm. We demonstrate the effectiveness of the proposed SpMV methods on an extensive dataset of real-valued large sparse matrices from the SuiteSparse Matrix Collection using an NVIDIA V100 GPU.
Erhan Tezcan, Tugba Torun, Fahrican Kosar, Kamer Kaya, Didem Unat
SBAC-PAD2
2018 Improving Medium-Grain Partitioning for Scalable Sparse Tensor Decomposition
abstract
Tensor decomposition is widely used in the analysis of multi-dimensional data. The canonical polyadic decomposition (CPD) is one of the most popular decomposition methods and commonly found by the CPD-ALS algorithm. High computational and memory costs of CPD-ALS necessitate the use of a distributed-memory-parallel algorithm for efficiency. The medium-grain CPD-ALS algorithm, which adopts multi-dimensional cartesian tensor partitioning, is one of the most successful distributed CPD-ALS algorithms for sparse tensors. This is because cartesian partitioning imposes nice upper bounds on communication overheads. However, this model does not utilize the sparsity pattern of the tensor to reduce the total communication volume. The objective of this work is to fill this literature gap. We propose a novel hypergraph-partitioning model, CartHP, whose partitioning objective correctly encapsulates the minimization of total communication volume of multi-dimensional cartesian tensor partitioning. Experiments on twelve real-world tensors using up to 1024 processors validate the effectiveness of the proposed CartHP model. Compared to the baseline medium-grain model, CartHP achieves average reductions of 52, 43 and 24 percent in total communication volume, communication time and overall runtime of CPD-ALS, respectively.
Seher Acer, Tugba Torun, Cevdet Aykanat
IEEE Trans. Parallel Distributed Syst.2