Demo Data from VLDB 2026 / reviewers in the wild / expert
Camille Negrevergne
dblp:23/1407
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2008
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Emerging computing paradigms · 100% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Emerging computing paradigms › quantum computer architecture
quantum circuit optimization |
0.1 | 1 | 2008 | Quantum Circuit Simplification and Level Compaction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008 |
Emerging computing paradigms
quantum computer architecture |
0.1 | 1 | 2008 | Quantum Circuit Simplification and Level Compaction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008 |
Methods — techniques the papers use, named apart from their topics
template matching · 0.1local optimization · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2008 | Quantum Circuit Simplification and Level CompactionabstractQuantum circuits are time-dependent diagrams describing the process of quantum computation. Usually, a quantum algorithm must be mapped into a quantum circuit. Optimal synthesis of quantum circuits is intractable, and heuristic methods must be employed. With the use of heuristics, the optimality of circuits is no longer guaranteed. In this paper, we consider a local optimization technique based on templates to simplify and reduce the depth of nonoptimal quantum circuits. We present and analyze templates in the general case and provide particular details for the circuits composed of NOT, CNOT, and controlled-sqrt-of-NOT gates. We apply templates to optimize various common circuits implementing multiple control Toffoli gates and quantum Boolean arithmetic circuits. We also show how templates can be used to compact the number of levels of a quantum circuit. The runtime of our implementation is small, whereas the reduction in the number of quantum gates and number of levels is significant. Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller, Camille Negrevergne |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 4 |