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Alan Dunworth

dblp:23/1885 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1979
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 86% Performance modeling and evaluation · 11% Embedded and real-time systems · 3%

Topics — the 2 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
logic synthesis
0.011979
An Efficient State Minimization Algorithm for Some Special Classes of Incompletetly Specified Sequential Machines · IEEE Trans. Computers 1979
Electronic design automation › logic synthesis › sequential circuit optimization
sequential machine minimization
0.011979
An Efficient State Minimization Algorithm for Some Special Classes of Incompletetly Specified Sequential Machines · IEEE Trans. Computers 1979

Methods — techniques the papers use, named apart from their topics

compatible pairs-table analysis · 0.0analytical modeling · 0.0
YearPublicationVenuePosition
1979 An Efficient State Minimization Algorithm for Some Special Classes of Incompletetly Specified Sequential Machines
abstract
Two classes of incompletely specified sequential machine (ISSM) are described, which contain the class of input-restricted machines defined by McCluskey [1] and Unger [2] as special cases. These new classes of machine can be identified at the conclusion of a modified (and more efficient) version of the standard compatible pairs-table analysis of Paull and Unger [3]. For such machines only maximal compatible classes need be considered in finding the minimal state machine, and any such covering selection is also closed. An algorithm is presented which is fast and efficient both for hand-use and computer implementation.
Alan Dunworth, H. V. Hartog
IEEE Trans. Computers1
1969 The Error Characteristics of the Binary Rate Multiplier
abstract
The binary rate multiplier is a device which has been used for many years in hybrid computing (operational digital techniques) and control systems as a means for generating a pulse train of average frequency proportional to the value of a binary number stored in a register. In general, the pulse spacing is irregular and the number of pulses generated in a given time fluctuates above and below the number which would be produced by a perfectly regular pulse train at the same average frequency. These fluctuations constitute a short-term frequency error, the value of which is an important parameter in the design of pulse rate digital systems incorporating binary rate multipliers. This article analyzes the conditions under which maximum positive and negative errors occur, and expressions are derived from which the magnitude of such errors may be calculated.
Alan Dunworth, J. I. Roche
IEEE Trans. Computers1