As integrated circuit technology continues to scale into the nanometer regime, the effect of crosstalk on circuit timing becomes significant. Static timing analysis shows that crosstalk routinely adds 10% to 20% delay to the critical path of a design. However, many aggressor/victim switching combinations are infeasible due to inherent circuit operating constraints, thereby contributing to the mismatch between timing analysis and actual silicon performance. This paper proposes a novel timing analysis technique where circuit functionality, delay, and crosstalk are simultaneously considered using time-sliced Boolean logic. The worst case timing on the critical path end point is calculated to be the minimum and maximum time slices where the timed Boolean logic on its coupled fanin cone is satisfiable. Up to 1-ns reduction in timing pessimism on 0.13-/spl mu/m industrial designs was observed. Furthermore, results on special circuit topologies such as data busses with coupled interleaved inverters match well with results from exhaustive Spice simulation sweeps with up to 50% reduction in timing pessimism over timing analysis that does not consider false coupling.

In This work we present a robust and efficient methodology for crosstalk-induced delay change analysis for ASIC design styles. The approach employs optimization methods to search for worst aggressor alignment, and it computes crosstalk induced delay change on each stage considering an impact on downstream logic. Computational efficiency is achieved using pre-characterized current models for drivers and compact macromodels for interconnect. The proposed methodology has been implemented in a commercial noise analysis tool. Experimental results obtained on industrial designs demonstrate high accuracy and reduced pessimism of the proposed methodology.

As processing technology scales down to the nanometer regime, capacitive crosstalk is having an increasingly adverse effect on circuit functionality, leading to increasing number of chip failures. In this paper, we propose mapping the static crosstalk functional noise problem into the well understood static timing problem. The key differences between static noise and static timing analyses, namely the injection of noise, accurate noise window propagation and register sensitive window computation are the contributions of this work. We demonstrate the effectiveness of this approach in two industrial designs by achieving 5X reduction in functional noise failures over noise propagation without considering timing of the composite noise pulse envelope, and 30X reduction in functional noise failures over net based noise failure metrics.