Renaud Gillon

dblp:23/2258 · DBLP profile ↗
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5ranked-venue papers
0as first author
2since 2021 · last 2024
0000-0003-0980-5238ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 2 since 2021Software engineering, systems software and programming languages · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 87% Hardware reliability and fault tolerance · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
fault simulation
0.812024
Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Electronic design automation
hardware verification and test
0.812024
Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Hardware reliability and fault tolerance
functional safety
0.212024
Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024

Methods — techniques the papers use, named apart from their topics

systematic literature review · 0.8PRISMA · 0.8
YearPublicationVenuePosition
2024 Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review
abstract
Since the last century, the exponential growth of the semiconductor industry has led to the creation of tiny and complex integrated circuits, e.g., sensors, actuators, and smart power. Innovative techniques are needed to ensure the correct functionality of analog devices that are ubiquitous in every smart system. The ISO 26262 standard for functional safety in the automotive context specifies that fault injection is necessary to validate all electronic devices. For decades, standardization of defect modeling and injection mainly focused on digital circuits and, in a minor part, on analog ones. An initial attempt is being made with the IEEE P2427 draft standard that started to give a structured and formal organization to the analog testing field. Various methods have been proposed in the literature to speed up the fault simulation of the defect universe for an analog circuit. A more limited number of papers seek to reduce the overall simulation time by reducing the number of defects to be simulated. This literature survey describes the state-of-the-art of analog defect injection and fault simulation methods. The survey is based on the Preferred Reporting Items for Systematic Reviews and Meta-Analyses (PRISMA) methodological flow, allowing for a systematic and complete literature survey. Each selected paper has been categorized and presented to provide an overview of all the available approaches. In addition, the limitations of the various approaches are discussed by showing possible future directions.
Sadia Azam, Nicola Dall'Ora, Enrico Fraccaroli, Renaud Gillon, Franco Fummi
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4
2023 Verilog-A Implementation of Generic Defect Templates for Analog Fault Injection
abstract
With functional safety being increasingly important in the development of mixed-signal products for automotive applications, EDA solutions have appeared striving to help designers in the setup and execution of fault injection campaigns. Despite the ongoing work to standardize the definition of defect models and coverage calculation methods in the IEEE P2427 draft standard, there is a lack of a unified and portable method to define defect templates that can be used to inject in a systematic way defects in an analog circuit. Each of the existing EDA tool sets for fault injection proposes its own proprietary method to specify how defects should be defined and injected. The proposed paper describes a Verilog-A-based approach to coding defect templates, which through compliance with the Verilog-A standard, warrants portability across compatible simulators. The approach has been validated on the circuits from the Analogue Benchmark Circuits made available by the IEEE P2427 working group.
Nicola Dall'Ora, Sadia Azam, Enrico Fraccaroli, Renaud Gillon, Franco Fummi
ACM Great Lakes Symposium on VLSI4
2016 Model Order Reduction for nanoelectronics coupled problems with many inputs
Nicodemus Banagaaya, Lihong Feng, Wim Schoenmaker, Peter Meuris, Aarnout Wieers, Renaud Gillon, Peter Benner
DATE6
2016 Electrothermal simulation of bonding wire degradation under uncertain geometries
Thorben Casper, Herbert De Gersem, Renaud Gillon, Tomás Gotthans, Tomas Kratochvil, Peter Meuris, Sebastian Schöps
DATE3
2013 SMAC: Smart Systems Co-design
abstract
In this paper we present the concepts and the organization of the FP7 Project SMAC (Smart systems Co-design), an Integrated Project (IP) of the 7th ICT Call under the Objective 3.2 "Smart components and Smart Systems integration". We describe in particular the project objectives and its organization, and how it addresses the challenges of the integration of heterogeneous and conflicting domains that emerge in the design of smart systems. The main outcome of the SMAC project is the development of flexible software platform (the SMAC platform) for smart subsystems/components design include methodologies and EDA tools enabling multi-disciplinary and multi-scale modeling and design, simulation of multi-domain systems, subsystems and components at all levels of abstraction, system integration and exploration for optimization of functional and non-functional metrics.
Nicola Bombieri, Giuliana Drogoudis, Giuliana Gangemi, Renaud Gillon, Enrico Macii, Massimo Poncino, Salvatore Rinaudo, Francesco Stefanni, Dimitrios Trachanis, Mark van Helvoort
DSD4