In this paper, an implementation of unification using a systolic-like method is presented for a VLSI-oriented Prolog machine. Not pointers but a line of symbols and the arity of each symbol are used to express the structure of terms on a uniformly structured cellular hardware. This data structure is demanded by the systolic-like method. Using the systolic-like method, copying structure, and occur check are easily executed during the process of unification. Moreover, searching variable is executed in parallel using a broadcast bus.

Any relations among finite fields can be transformed to a unique polynomial of one variable using Galois Fields. In this paper, we explain the design for a "Polynomial Transformer" which executes the transformation. Polynomial Transformer consists of very simple and iterative logic, and it is very suitable for parallel and pipelined VLSI algorithm. Moreover, three dimensional construction of a Polynomial Transformer is possible. Thus, it serves as an example of a typical three dimensional VLSI. Its application can be found in Polynomial Transformation, disturbance of data and so on.

article Free Access Share on (SM)2-II: a new version of the sparse matrix solving machine Authors: Hideharu Amano Department of Electrical Engineering, Keio University, Yokohoma 223 Japan Department of Electrical Engineering, Keio University, Yokohoma 223 JapanView Profile , Taisuke Boku Department of Electrical Engineering, Keio University, Yokohoma 223 Japan Department of Electrical Engineering, Keio University, Yokohoma 223 JapanView Profile , Tomohiro Kudoh Department of Electrical Engineering, Keio University, Yokohoma 223 Japan Department of Electrical Engineering, Keio University, Yokohoma 223 JapanView Profile , Hideo Aiso Department of Electrical Engineering, Keio University, Yokohoma 223 Japan Department of Electrical Engineering, Keio University, Yokohoma 223 JapanView Profile Authors Info & Claims ACM SIGARCH Computer Architecture NewsVolume 13Issue 3June 1985 pp 100–107https://doi.org/10.1145/327070.327137Published:01 June 1985Publication History 16citation208DownloadsMetricsTotal Citations16Total Downloads208Last 12 Months7Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

In this paper a parallel and piplined fast matrix equation solver in GF(2) is proposed where the elements are 0s or 1s. The solver employing the iterative logic circuits which are suitable for VLSI implementation can be realized by the conventional Gauss Jordan Elimination Method. O(n) gate stages in the pipeline and O(n3) total gates are required for solving A X = b where A is a matrix of n×n, X and b are vectors respectively. The organization of the solver is discussed in this paper.

In analyzing electronic circuits, it is usually necessary to solve simultaneous linear equations which provide with a sparse coefficient matrix. In order to treat these problems effectively, we propose a dedicated parallel machine called 'Sparse Matrix Solving Machine', or (SM)2 for short.

This paper discusses the role of microprogramming in operating system design and shows several things: (1) advantages of the efficiency which may be gained from microcoded operating system primitives, (2) selecting the most appropriste primitives for implementation, and (3) an analysis of the tradeoffs among software, firmware, and hardware. The authors propose a practical approach of enhancing computer architecture level, from a view point of functional hierarchy of operating systems. In order to prove the advantages of this approach, we have designed and implemented an experimental abstract machine for an operating system nucleus. This research is an experimental design, and evaluation on its operating system nucleus machine,called HEART. HEART is a set of primitive and universal functions, and works as a nucleus of a multiprogrammed operating system. The research results of our approach are the followings: First, to clarify the properties of operating system nucleus, taking functional hierarchy of operating system into consideration. Second, to show the design of operating system nucleus based on novel concepts. Third, to confirm the possibility of implimenting operating system nucleus machine. Finally, we give a performance evaluation on microcoded HEART and the effectiveness of enhancing computer architecture level based on the properties of operating systems.

This paper deals with an automatic recovery mechanism designed to prevent the occurrence of subtract errors at the computer architecture level. This mechanism always detects the occurence of subtract errors whenever addition or subtraction is performed. If a subtract error is detected, backtracking to a certain location is carried out, and from there recomputing is performed in order to realize the required precision. An adaptive algorithm required for this mechanism is described in detail. An experimental adaptive computer was implemented on a Burroughs B1700. The evaluation of the experiments proves that the inherent possibilities of dynamic microprogramming play a very important role in realizing this mechanism, and that the proposed mechanism will be useful for the development of future high-level computer systems.