The increasing complexity of safety-critical hardware systems demands advanced methods for ensuring functional safety (FuSa). Traditional techniques like ATPG and BIST are intrusive, requiring additional hardware and disrupting operations, making them unsuitable for in-field testing. To address this, for the first time, we propose a machine learning (ML)-driven automated Self-Test Library (STL) generation for seamless in-field testing during idle periods, ensuring uninterrupted fault detection and high system performance. Utilizing reinforcement learning, the STL generates design-specific test patterns, achieving up to $57.57 \%$ improvement in fault coverage and up to $85 \%$ efficiency compared to existing pattern-based testing, enhancing FuSa in mission-critical applications.

Safety-critical applications such as autonomous driving demand rigorous functional safety assurance. We present a safety-guided test pattern generation framework called NeuralTPG for transition faults in integrated circuits (ICs) based on Launch-on-Capture (LOC) delay testing. We model the logical state transition behavior of standard cells using multilayer perceptrons (MLPs), referred to as Cell-Nets. The neural twin is constructed by converting standard cell instances into Cell-Nets and replacing inter-cell wires with neural connections. We leverage the end-to-end differentiability of the neural twin to compute input test-pattern pairs for transition faults through back-propagation. The neural twin enhances fault propagation to primary outputs (POs) and generates test-pattern pairs that maximize faults’ propagation capability. The framework supports non-binary, user-defined criticality-factor (CF) assignment across the circuit’s internal nets and POs, enabling CF-guided test-pattern pair generation to propagate transition faults to more critical POs. NeuralTPG employs concurrent test generation, fully leveraging GPU acceleration to generate test-pattern pairs for all transition faults simultaneously, thereby improving test efficiency. Experimental evaluations on six benchmarks across three CF configurations demonstrate that NeuralTPG can be used to achieve safety-guided fault propagation.

Integration of analog and RF circuits with advanced node digital systems has leapfrogged analog circuits by several technology nodes. This has resulted in higher defect rates as well as higher process variations. Another point of pressure is that some application domains, such as the automotive industry, require very low defect rates. To ensure that the circuits are thoroughly tested without increasing the test cost severely, test optimization methods can be applied. Examples of test optimization can include the use of alternate tests, reduced test sets, and built-in self-tests. Defect coverage of the optimized tests needs to be evaluated to ensure high-quality products. For analog circuits, defect definitions are generally continuous and minimum detectable deviation (of hard and soft defects) may differ from one test to another. Finding this detectability point is important to compare potential test conditions. In this paper, we propose an algorithm to determine the minimum detectable defect severity for each defect under given test conditions. Ultimately, this information can be used to find the most sensitive test method that already covers the detection limit of other methods. Experiments on an 8-bit ADC circuit show that the proposed algorithm finds the defect detectability limits of different test methods in only a few search steps and yields accurate results.

The increasing complexity of Electrical and Electronic (E/E) systems underscores the need for protective measures to ensure functional safety (FuSa) in high-assurance environments. This entails the identification and fortification of vulnerable nodes to enhance system reliability during mission-critical scenarios. Traditionally, the assessment of E/E system reliability has relied on fault injection (FI) techniques and simulations. However, FI faces challenges in coping with escalating design complexity, including resource demands and timing overheads. Furthermore, it falls short in identifying critical components that may lead to functional failures. To address these challenges, we propose a Machine Learning (ML)-based framework for predicting critical nodes in hardware designs. The process begins with constructing a graph from the design netlist, forming the foundation for training a Graph Convolutional Network (GCN). The GCN model utilizes graph node attributes, node labels, and edge connections to learn and predict critical nodes in the circuit. The model furnishes up to 93.7% accuracy in identifying vulnerable circuit nodes during evaluation on diverse designs such as Synchronous Dynamic Random Access Memory (SDRAM) controller, OpenRISC 1200 (OR1200) modules. Furthermore, we incorporate an explainability analysis to interpret individual node predictions. This analysis discerns the critical design factors influencing fault criticality in the design. Moreover, to the best of our knowledge, we, for the first time, perform a regression analysis to generate node criticality scores, quantifying the degrees of criticality, that can enable prioritizing resources towards critical nodes.

The objective of fault simulation is to estimate the fault coverage of a given test input. Established fault models in the analog domain are based on detailed transistor-level netlists. Existing fault simulation tools inject and analyze fault responses at this level of detail. However, extending fault simulation to large circuits, especially when digital signals and/or frequency translation is involved, can be difficult due to the nature of simulations. Designers work with models at higher abstraction levels where simulations are more efficient. The goal of this paper is to bridge the gap between available transistor-level fault simulation tools, where fault simulation can be accurate, and behavioral abstraction levels, where simulation time can be shorter. We aim to achieve this by judiciously adding various functional enhancements to individual functional blocks from a list of templates into their behavioral model until the responses at the two abstraction levels match. Transistor-level simulations are only limited to smaller functional blocks, where they are feasible, and individual fault responses are captured for behavioral simulations. Experimental results on two example circuits, a flash ADC and a PLL, show that accurate simulations can be achieved at a fraction of the simulation time.

Many real-life safety-critical applications such as autonomous driving require functional safety. We present a framework for functional safety-guided test pattern generation. We incorporate the functional information of each standard cell into a multi-layer-perceptron (MLP), referred to as Cell-Net. Each Cell-Net is a pre-trained MLP that models the behavior of the corresponding standard cell. The design netlist is translated into its neural twin, where the standard cell instances are substituted by their corresponding Cell-Nets and the wires in the netlist translate to neural connections between these Cell-Nets. We leverage the neural twin-enabled back-propagation for gradient computation, and utilize these gradients to compute test patterns. The output of every Cell-Net is associated with a bias that represents a perturbation in the signal propagating through that Cell-Net. We manipulate these bias values to inject stuck-at faults at the output of Cell-Nets. We utilize the neural twin to enhance the propagation of faults to primary outputs (POs), and find the test patterns that maximize the propagation of faults to POs. The neural twin also enables the assignment of non-binary criticalityfactors (CFs) to different POs and perform a test-pattern search for each fault for a given CF configuration. Our results on five benchmark circuits across three different CF configurations show an increased fault propagation achieved by the neural twin as compared to Automatic Test Pattern Generation (ATPG).

OverviewThere are two presentations in this session which describe non-conventional test methods. The first presentation is about testing micro-mirror devices used for imaging and light projection applications. The second presentation is about new directions in testing radar devices. Together they highlight new challenges in testing these systems in the context of the applications that they are incorporated into.

As the use of safety critical systems is becoming more prevalent, there is a need to reduce the implementation overhead required to provide safety. The conventional design of such systems does not consider application behaviours, thereby resulting in a pessimistic design where the safety provided is often not required during large periods of the application execution. In this paper, we analyse the different phases of an application during its overall execution life cycle, together with the embedded threads to perform specific operations, and propose a new methodology for protection of the safety critical application threads. We show the benefits of this method and the ability to build lower cost systems which are functionally safe using the flexibility which is embedded inside the application itself. Two new application based protection schemes, based on altering the application execution parameters (e.g. control loop frequency) and redundant execution of selective threads, are proposed. For these experiments, we have used commercial off the shelf components without any hardware functional safety features and implemented safety measures by augmenting the application software. Experiments on Electric Vehicle Traction (EVT) and On-Board Charger (OBC) applications indicate overall MIPS savings between 70% to 95%. These results indicate that a careful design of the application can itself be the first step to protect the integrated circuits which drive them.

High resolution ADCs employing histogram test for linearity measurement suffer from high test time. This test time is an important factor in determining the overall cost of the ADC. While alternate test methods for linearity checks in the presence of static errors have been proposed, no low cost test method for the detection of dynamic errors has been reported so far. This paper analyzes dynamic errors in SAR ADCs and proposes a test method to detect these errors. This algorithm, when combined with the previously reported uSMILE (ultra fast segmented model identification of linearity errors), gives better noise averaging capability than the conventional histogram test. By applying constrained polynomial fit technique over strategic points in the reduced hits per code histogram data, we are able to suppress the effect of noise in the histogram test and thus, accurately detect dynamic errors. Results on a sample set of 50 devices of a 12 bit ADC indicate an excellent match between the sine histogram test with 240 hits per code for linearity measurement and the proposed method with just 4 hits per code.

Many real-life systems have integrated circuits interacting with physical systems in safety critical applications. These systems are called hybrid systems. The safety analysis of integrated circuits used in such systems is typically done in isolation of the end application and associated physical system, and hence results in the need to take recourse to conservative design techniques utilizing costly redundancy. We are gradually moving away from the paradigm of independently designing the digital and physical parts of hybrid systems towards simultaneous considerations for both. These systems have an acceptable tolerance determined by the application due to the inertial nature of the physical system, error tolerance capability in closed loop applications, built-in hardware and software functionality, etc. In this paper, we perform a comparative study of integrated circuit safety analysis as practiced today and system level application specific safety analysis that incorporates a physical system. We propose an improved method based upon the divide and conquer approach for such co-analysis to address practical limitations associated with adopting system level analysis techniques during integrated circuit design. Experimental results for a representative motor control system indicate that the application has an error tolerance of 92–160 cycles of closed loop operation for worst case errors and a control value error tolerance in the range of 5–7% at different operating conditions. Incorporation of application tolerance results in up to 4.3X reduction in the number of hardware elements which need to be protected.

Industry continues to grapple with analog test in terms of the right set of parameters to be tested and the right set of tests and measurements required for them. On one hand, is the growing analog content in today's ICs, and on the other, is the need to optimise test and characterization to make it affordable and timely across different quality and reliability requirements laid down by the application markets. Different companies and teams have often used their own internal custom methods to simplify analog test with varying demands on test and automation, resulting in varying degrees of success. In this innovative practices session, the three presentations are from three leading semiconductor companies, and they illustrate their approach to simplifying analog test. They cover different topics ranging from enablers for adoption of structural test methods to how the ATE can scale to match with the DUT high speed interfaces, and the modifications needed in the test flow to leverage the results from new validation and BIST methods.

Small delay defect (SDD) ATPG has been around for a few years now; however, its adoption is not prevalent due to various reasons. (i) Unique detection with SDD ATPG patterns over transition delay fault (TDF) ATPG patterns is often not easy to establish due to the large volume of the former and the insistence on coverage due to the latter. (ii) Lack of a seamless method to target SDD patterns for nodes which are embedded in paths with small slack and TDF patterns for the other nodes further inhibits SDD ATPG. In this paper, we present methods to address both these limitations. We describe a method for targeted SDD pattern generation for SDQL (statistical delay quality level) improvement across logic modules in multiple clock domains (at different frequencies) based on slack intervals. We also describe a method to incorporate patterns corresponding to other fault models suitably (namely TDF and PDF - path delay fault) to improve the SDQL metric without significant pattern volume inflation. Results on a large SOC indicate a reduction in the test pattern volume ranging from 45% to 92%, and an SDQL improvement ranging from 48% to 85%, as compared to standard methods in use today.

As integrated circuits become increasingly complex, the fabrication process renders them more marginal to specification parameters. Consequently, these circuits have to be tuned post fabrication to compensate for process marginality and thereby optimize their performance as well as to improve yields. This process of tuning is commonly termed as trimming, wherein the right set of digital trim codes is identified and used as a calibration setting by writing these codes into the hardware configuration registers. This paper addresses the problem of carrying out multi-variable trims involving two or more parameters, codes for which must be simultaneously searched and set, in order to attain the desired performance of the circuit. A novel low-cost hardware implementation of the Simplex minimization algorithm with speed-up improvements is described. This implementation is amenable for on-chip BIST (built-in self-test) and can also be directly implemented as part of the ATE (automatic test equipment) program. Experimental results are presented on two industrial circuits. Improvements in terms of trim code search time and attaining better performance are shown.

Integrated circuits are being used in different applications which are not always known at the time of specification and design creation. Safety standards specify that certain design processes be followed to guarantee safety of the applications in which these circuits are being used. As a result, the design phase is followed (often mandated) by an evaluation phase, wherein the safety worthiness of the circuit must be ascertained. In this paper, we perform a detailed study of such an evaluation as practised in the industry, understand the limitations, and propose techniques to improve the existing methodology. The improvements proposed are: (i) Capturing workload diversity as input constraints (values and sequence). (ii) Modelling application specific performance tolerance. (iii) Illustrating how physical system can be included into this analysis using a suitable representation. (iv) Budgeting of tolerance across various interacting modules to reduce computational complexity of safety analysis. Experimental results to illustrate suitability of the proposed methods are presented using a set of ITC benchmark circuits and two representative industrial circuits.

Dynamic voltage-frequency scaling (DVFS) is used in system-on-chips (SoCs) for power management, but it increases test time because every core must be tested at multiple voltage settings. In addition, testing at lower power supply voltage settings increases the length of each test due to the corresponding reduction in frequencies that can be used for scan shift operations. Existing test scheduling techniques do not consider test applications at multiple voltage settings, therefore they are not effective for reducing test time for DVFS-based SoCs. We propose a time-division multiplexing (TDM) architecture, which uses the highest available frequency for shifting test data into the SoC and then distributes the test data into multiple cores using lower shift frequencies. TDM is accompanied by three test scheduling methods, which are suitable for different scenarios: 1) an integer linear programming-based formulation that offers optimal results for SOCs of moderate size; 2) a greedy approach that provides good results with very short run time even for very large SoCs; and 3) a rectangle-packing approach combined with simulated-annealing that offers a trade-off between run time and test-time reduction for all SoCs. Experimental results on two industrial SoCs highlight the effectiveness of TDM and the associated scheduling methods.

Even though system-on-chip (SoC) testing at multiple voltage settings significantly increases test complexity, the use of a different shift frequency at each voltage setting offers parallelism that can be exploited by time-division multiplexing (TDM) to reduce test length. We show that TDM is especially effective for small-bitwidth and heavily loaded test-access mechanisms (TAMs), thereby tangibly increasing the effectiveness of multi-site testing. However, TDM suffers from some inherent limitations that do not allow the fullest possible exploitation of TAM bandwidth. To overcome these limitations, we propose space-division multiplexing (SDM), which complements TDM and offers higher multi-site test efficiency. We implement space-and time-division multiplexing (STDM) using a new, scalable test-time minimization method based on a combination of bin packing and simulated annealing. Results for industrial SoCs, highlight the advantages of the proposed optimization method.

It is well-known that complex SOCs with RF and embedded power management (PM) modules require significant post manufacturing calibration to ensure that the device meets the design specifications. These calibrations are carried out by setting the register bits (which in turn help to finely adjust the parameters of the components inside the module containing these registers), a process commonly termed as trim. Not only must these calibrations precede any other manufacturing test operation, but they also require analog measurements and consume significant ATE resources and hence test time. As a result, it is commonly understood and observed that the calibration trim for such SOCs with embedded RF and PM is often comparable to the SOC test time itself. This paper presents some crucial investigations into one such 45 nm multi-core RF SOC designed at Texas Instruments. Its main contributions are: (i) The various trim operations are analyzed for the incurred test times and incurred ATE resources. (ii) Corresponding to each such operation, trim test time minimization techniques are proposed and experimental data on the accrued benefits is presented. (iii) A comprehensive hardware trim BIST controller is described, which enables trim automation and further optimization in complex SOCs. Together, these investigations provide a recipe for efficiently performing trims in complex mixed-signal SOCs with reduced test times and higher ATE enabled multi-site.

This paper discusses how adaptive test techniques can be applied to multi-core RF SoCs, together with design implementation and test challenges. Various techniques specific to RF circuits covering calibration trims, power management modules, co-existence issues, concurrent testing, and test measurements are explained. Results on different designs are presented. Together, they highlight the need and scope of adaptive test for RF circuits, and share a new dimension in the test of multi-core circuits, under different constraints of design, test and test equipment.

Dynamic voltage scaling (DVS) has been widely adopted in multicore SoCs for reducing dynamic power consumption. Despite its benefits, the use of DVS increases test time because high product quality can only be ensured by testing every core at multiple supported voltage settings; hence the repetitive application of the same or different tests at multiple voltage settings becomes necessary. In addition, testing at lower supply voltage settings increases considerably the length of each test because lower scan frequencies must be used for shifting test data using scan chains. Standard scheduling techniques fail to reduce the test time for DVS-based SoCs since they do not model testing at multiple voltage settings. In addition, they do not consider the practical aspects of tester overhead and the dependencies between core voltage settings due to the use of voltage islands. To alleviate the detrimental impact of DVS on test application time, we propose a time-division multiplexing (TDM) method and an integer linear programming-based test scheduling technique, which exploit high automatic test equipment (ATE) frequencies even when low shift frequencies must be used at low voltage settings. Experimental results on two industrial SoCs highlight the effectiveness of TDM and the associated scheduling method.

Ensuring reliable operation over an extended period of time is one of the biggest challenges facing present day electronic systems. The increased vulnerability of the components to atmospheric particle strikes poses a big threat in attaining the reliability required for various mission critical applications. Various soft error mitigation methodologies exist to address this reliability challenge. A general solution to this problem is to arrive at a soft error mitigation methodology with an acceptable implementation overhead and error tolerance level. This implementation overhead can then be reduced by taking advantage of various derating effects like logical derating, electrical derating and timing window derating, and/or making use of application redundancy, e.g. redundancy in firmware/software executing on the so designed robust hardware. In this paper, we analyze the impact of various derating factors and show how they can be profitably employed to reduce the hardware overhead to implement a given level of soft error robustness. This analysis is performed on a set of benchmark circuits using the delayed capture methodology. Experimental results show upto 23% reduction in the hardware overhead when considering individual and combined derating factors.

In order to provide high performance with low power consumption, many multicore chips employ dynamic voltage scaling and voltage islands that operate at multiple power-supply voltage levels. Effective defect screening for such chips requires test applications at different operating voltages, which leads to higher test time and test cost compared to systems-on-a-chip (SoCs), which operate at only a single voltage level. We propose test scheduling techniques to minimize the testing time for multicore chips when each core is tested at multiple voltage levels and when it is tested for state retention when the core switches between two voltage levels. The proposed techniques include exact optimization based on integer linear programming and fast heuristic methods. Experimental results for two test-case SoCs from the industry highlight the effectiveness of the proposed method.

In order to provide high performance with low power consumption, modern multicore chips employ dynamic voltage scaling and voltage islands that operate at multiple power-supply voltage settings. Effective defect screening for the embedded cores in such multicore chips requires test application at their different operating voltages, which leads to higher test time and test cost. We propose a fast heuristic test scheduling technique for multicore chips that minimize the testing time when each core is tested at multiple voltage settings as well as if it is tested for state retention when the core switches between two voltage levels. Experimental results for two test-case SOCs from industry highlight the effectiveness of the proposed method.

Soft errors are one of the biggest reliability challenges for present day electronic devices. With technology scaling, the contribution of soft errors to overall device failure is on the rise and it is becoming the dominant reliability failure mechanism. Several techniques exist for the detection and correction of soft errors. Reducing implementation overhead is one of the areas which researchers were focusing on, and several optimization techniques are being proposed. In this paper, we propose a novel methodology, using error detection and correction codes to reduce the implementation overhead. We extend the earlier work on delayed capture methodology, and divide the total number of flip-flops into various groups and calculate the check bits for each group. This method exploits the reduction in the fault space which is generated due to single event upsets, and illustrates how the detection and correction implementation overheads can be minimized. Experimental results highlight the effectiveness of this technique. As compared to the original implementation, 44.80% reduction in area is obtained, without sacrificing the coverage.

Mixed signal SOCs with integrated RF and power management modules have some distinct requirements associated with them. They are often used in portable and battery operated consumer applications, which are extremely cost and power sensitive. This translates into a few unique design and test constraints on the amount of DFT logic integrated, the permissible test time, and power-up of individual modules in the SOC. In this paper, we propose some novel DFT and test techniques which have been devised keeping in mind these constraints, and illustrate how test cost has been significantly reduced in such cost and power constrained mixed signal SOCs. The paper discusses three significant components of the test time and techniques for their reduction through smarter DFT and BIST: (i) RF tests in multiple radio modules, (ii) test and calibration of complex power management logic and voltage regulators, and (iii) improved scan ATPG for all the digital logic. These techniques are being integrated into Texas Instruments' embedded SOCs designed for such portable application, resulting in an overall test cost reduction by half over the previous generation of such SOCs.

ATPG tool generated patterns are a major component of test data for large SOCs. With increasing sizes of chips, higher integration involving IP cores and the need for patterns targeting multiple fault models for better defect coverage in newer technologies, the issues of adequate coverage and reasonable test data volume and application time dominate the economics of test. We address the problem of generating compact set of test patterns across multiple fault models. Traditional approaches use separate ATPG for each fault models and minimize patterns either during pattern generation through static or dynamic compaction, or after pattern generation by simulating all patterns over all fault models for static compaction. We propose a novel ATPG technique where all fault models of interest are concurrently targeted in a single ATPG run. Patterns are generated in small intervals, each consisting of 16, 32 or 64 patterns. In each interval fault model specific ATPG setups generate separate pattern sets for their respective fault model. An effectiveness criterion then selects exactly one of those pattern sets. The selected set covers untargeted faults that would have required the most additional patterns. Pattern generation intervals are repeated until required coverage for faults of all models of interest is achieved. The sum total of all selected interval pattern sets is the overall test set for the DUT. Experiments on industrial circuits show pattern count reductions of 21% to 68%. The technique is independent of any special ATPG tool or scan compression technique and requires no change or additional support in an existing ATPG system.

With the scaling of technology node and voltage levels, the susceptibility of logic to soft errors is increasing. Hence it is very important to take care of soft errors in the combinational logic along with those in the sequential elements. In this paper, a novel method is proposed to detect the presence of soft errors in both combinational and sequential logic. In this method, flip-flops are grouped and parity is computed for each group twice - once at the input of the flip-flops and next at the output. Later, the parity at the inputs and outputs is compared to detect the presence of soft errors. The effectiveness of the technique is shown through experimental results.

Wireless connectivity SOCs integrate multi-band radios on a single chip. Examples include WLAN 802.11 ("A" band or "BG" band), Bluetooth, Global Positioning System (GPS) and FM (Frequency Modulation) transmitters and receivers. It has been observed the cost of testing these RF components constitutes about 40% of the total cost of testing such an SOC. Reduction of this test cost is, therefore, important. The usage of multiple radios on a single chip provides the option of testing all of them concurrently. The unique functionality and different frequency bands of these radio modules however, prevent blind (unconstrained) parallelism, something which is ubiquitously possible for digital logic and memory modules. Additionally, the ability to test multiple dies in parallel (multi-site testing) and the ability to adopt low-cost tester platforms must also be considered. In this presentation, a case study of a complex SOC with four such radio modules is presented. It is shown how their concurrent test can be planned, together with high levels of multi-site with a low-cost tester platform. Various considerations and tradeoffs in the adoption of this solution are discussed, keeping in mind co-existence and coupling issues when these radios operate in parallel. The software BIST solution (where firmware is executed on a host processor inside the RF module) used to enable such concurrency is also explained, together with the design support required.

Test costs continue to rise as designs become more complex, the controllability and observability points at the chip boundary reduce, defects become more subtle making it harder to detect them, and reliability requirements become stringent. While several techniques have been developed and deployed to contain test costs to remain within acceptable limits, new technologies tend to generate excursions where the costs once again become prominent. Digital circuits have benefitted from structured test methodologies (involving DFT, ATPG and BIST) wherein different optimizations have been incorporated to reduce test costs. Analog circuits have also received wide attention due increasing analog content in today's chips. DFT techniques for them have evolved to provide additional controllability and observability through additional on-chip / off-chip instrumentation. Digitization of the analog stimuli and response have also been considered adequate to ascertain the correctness of analog circuits. RF circuits, on the other hand, have a few characteristics which have rendered such simplification so far inadequate. (i) The stimuli and response can be greatly deformed due to attenuation at the high frequencies at which the transmission occurs over the tester channels. (ii) Multiple RF modules in a chip cause further interference, thereby impairing the measurement resolution attainable for test. (iii) While on-chip instrumentation for test and measurement is even more important, providing it itself largely uneconomical. (iv) There is virtually little automation (EDA tools, etc.) available today to address these issues. Hence, though RF circuits are just an extension of analog / mixed-signal circuits in the high frequency range, their test poses several new challenges, which have hitherto not been adequately solved.

Shrinking power budgets in low power system-on-chips (SoCs) have elevated test power consumption as a major consideration for chip design and test engineering teams. Many traditional automatic test pattern generation (ATPG) and design-for-test (DFT) techniques for test power reduction are either effective for circuits not using test data compression hardware or have implications on the physical design cycle. This paper describes a technique for reducing peak current during scan based testing that can work in the presence of compression, and impose no restrictions on physical design, e.g. related to chip clocking. We propose low-design effort modifications to the test compression logic (wrapper-like changes) that enable us to (a) bypass scan chains or groups of them and (b) shift in constant values into the bypassed flip-flops for lowering the instantaneous current drawn. The modifications are easily localized to a scan chain wrapper that can be used with any scan compression solution. An SoC using low-power scan chain wrappers provides sufficient configurability (scan chains bypassed or scan chains included) to explore different power reductions with test cost trade-offs. We describe a methodology that allows us to manage the inherent configurability available in our solution. For empirical validation, we have implemented low-power scan chain wrappers for a subset of scan chains in a recently taped-out 65nm low-power SoC. We present experimental data from ATPG and initial silicon power measurements for this chip to demonstrate the benefits and limitations of the proposal.

We present a design-for-testability (DFT) technique for increasing the effectiveness of LFSR reseeding for unmodeled defects. The proposed method relies on seed selection using the output-deviations metric and the on-chip augmentation of seeds using simple bit-operations. Simulation results for benchmark circuits show that compared to LFSR reseeding using output deviations alone, the proposed method provides higher coverage for transition-delay and bridging faults, and steeper coverage ramp-up for these faults for the same number of seeds. For the same pattern count (and much fewer seeds), the proposed method provides comparable unmodeled defect coverage. In all cases, complete coverage of modeled stuck-at faults is obtained. We therefore conclude that high test quality can be obtained with the proposed LFSR reseeding method using a smaller number of seeds.

Periodic testing of electronic devices on the field during application execution is becoming increasingly important. In addition, some of these applications are embedded and real-time, requiring the system to be operational for extended periods. In such applications, field test must be cleverly interleaved with normal operation, such that the latter is not impacted, while at the same time guaranteeing the correct operation of the device, and identification of any malfunction or defects within a reasonable time. This paper discusses the design techniques and tradeoffs in implementing non-destructive field test using logic BIST self-test. Three specific designs aspects are discussed, namely (i) choice of logic BIST self-test architecture, (ii) optimizations in test time and additional memory requirements for attaining a given coverage, and (iii) DUT interface to self-test DFT logic to enable such form of test and application interleaving. Data is presented for an IP core, which is presently being designed in Texas Instruments (India), wherein such tests are being supported for use in automotive applications.

This paper examines the differences in power consumption characteristics of two popular ATPG techniques for transition fault testing (TFT) -- launch off shift (LOS) and launch off capture (LOC). These differences have critical implications on the circuit switching during the launch and capture cycles, and if unaddressed, can lead to IR drop issues and unwarranted silicon failures. Our investigations show that power consumption in the launch cycle for LOS patterns can be as high as 1.96 times the corresponding number for LOC patterns. We systematically understand the reasons for this difference and propose a variety of power-aware design-for-test (DFT) and automatic test pattern generation (ATPG) techniques to limit this power differential as well as general TFT power consumption. The proposed techniques include use of (a) fill techniques, (b) intelligent test and functional enable control of clock gates, and (c) pattern re-generation using low compression and low effort ATPG. Our experiments demonstrate the efficacy of the proposed techniques in reducing power consumption, and the associated trade-offs in pattern volume.

The use of scan based compression techniques is becoming mandatory on current designs. While high compression is desired to hold the test costs within limits, it is important to understand the bounds set by the entropy of the care bits required by different compression techniques, to enable the selection of the right set of design and test parameters. This paper highlights the available solution space for compression based designs and discusses the various parameters which result in test tradeoffs. The discussion is supported with elaborate experimental data. Through them, the paper offers an insight into the solution space of compression techniques and makes resulting recommendations.

With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double sampling checker (used in Razor), is the simplest and most area and power efficient, but suffers from very high false detection rates of 1.15 times the actual error rates. We also find that the alternate approaches of triple sampling and integrate and sample method (I&S) can be designed to have zero false detection rates, but at an increased area, power and implementation complexity. The triple sampling method has about 1.74 times the area and twice the power as compared to the Double Sampling method and also needs a complex clock generation scheme. The I&S method needs about 16% more power with 0.58 times the area as double sampling, but comes with more stringent implementation constraints as it requires detection of small voltage swings.

Automotive electronics today is characterased by two requirements. One is the well-known aspect of reliability of the components used to build the system. The other is the increasing need for commoditisation of these systems. These requirements pose the dual challenges of meeting very strict quality goals, while at the same time also adhering to affordable cost goals. Devices designed for one end application often find use in others. Consequently, it is important that these devices be designed and tested in a scaleable manner, wherein the high quality and low cost goals are simultaneously met. In this paper, a case study is presented on a set of recently designed automotive chips at Texas Instruments (India). Illustrations of different techniques are given, together with supporting data. These techniques are generic enough to be adopted and further improvised to enhance test cost and test quality optimisations in a larger class of SOCs as well.

Conventional methods to assess the test data volume (TDV) of logic in system-on-chips (SoCs) use intuitive formulae that are often agnostic of the target automatic test equipment (ATE) hardware or the ATE test program compilation process. In this paper, we first show that such ATE-unaware approaches lead to a significant gap between these estimates and the actual tester memory consumed. We also provide a generic solution to this problem by using statistical regression techniques to build an ATE-aware TDV model that accurately estimates test program memory consumption as a function of the design and test pattern characteristics. We have implemented this methodology using an off-the-shelf regression solver in the context of a production test flow. We show that the estimator can be used to compute TDV with very high accuracy for logic tests of various industrial IP cores and SoCs.

This paper proposes a new technique of power-aware test pattern generation, wherein the test mode power constraints are specified using pseudo hardware logic functions (referred to as power constraint circuits) that augment the target circuit fed to the ATPG tool. The novelty of this approach is three-fold: (i) The ATPG tool only sees the enhanced circuit. This influences the generation of the test cubes themselves, as against post-processing of these cubes for a given pattern. (ii) Pattern generation can be driven to minimize test power according to a programmable switching activity threshold, and hence, is scalable. (iii) The same constraint circuit can also be effectively used for pattern filtering to isolate patterns which cause high switching activity. Additionally, the proposed method does not require any changes to the pattern generation tool or process. This paper describes the methodology, together with techniques for realizing the hardware circuit and specifying thresholds. Experimental results on various benchmark circuits (including an industrial design) are presented to show the effectiveness of this approach.

In addition to static faults, dynamic faults are increasingly important for high density embedded memories due to aggressive design rules and shrinking feature sizes. Not only is the test of these faults important, their repair is important too for devices where the yield loss due to memory fails is significant. Dynamic faults can impact one or more memory cells. In the case of the latter, it is also important to diagnose the cell causing the fault, and hence to be repaired. This paper describes an on-chip test and repair solution for static and dynamic faults in random access memories. The main contributions of this paper are three fold: (i) development of new algorithms for detection of static and dynamic faults, and for identification of faulty aggressor cells, (ii) extension of fault syndromes for diagnosis and location of aggressor cells, and (iii) development of an on-chip test, analysis and repair solution implementing these algorithms. It is shown how the proposed fault detection algorithms and redundancy analysis schemes are superior to existing ones for analysis time, hardware overhead, fault coverage and aggressor location capability

Large designs, larger test pattern volumes and longer test times have necessitated the use of test data and test time compression techniques built around the scan design paradigm. The adoption of these techniques is increasing. Much as well as they are understood today, these techniques continue to present challenges in their adoption and implementation. As their adoption increases, new compression targets are set, in turn forcing the investigation of better solutions and upper bounds. In this Innovative Practices track session, implementation case studies for various scan compression techniques will be presented, together with their tradeoffs and entitlement. Emerging developments in these technologies will be described, together with some theoretical results and possibilities.

The generation, qualification and validation of structural patterns for transition and path delay faults present several problems due to various design, tools and tester constraints. This paper proposes a flow for the generation and selection of a reduced set of structural patterns for at-speed testing, based on pattern reuse across different fault models, and based on metrics of minimum single detect and a qualified N-detect coverage. Patterns generated using ATPG and deterministic BIST techniques are considered for large representative SOC designs. It is shown that significant reduction of up to 35% in the pattern volume is achieved without compromising the test quality. These pattern selection techniques are being deployed in different designs in Texas Instruments (India).

Growing test costs impact the design and implementation of large and complex IP (intellectual property) modules, (often reused as embedded cores), as well as the construction of SOCs (systems-on-chip) using them. The modules must be designed for re-use in different devices, and the SOCs using them too must be designed to support various end applications, with diverse requirements of performance, power, reliability and cost, within the constraints of the budgetted design and test costs and product development cycle times. These constraints often make the DFT (design for testability) process a very critical and differentiating component of the overall design cycle, as well as a key enabler for robust designs.

Verification of present day SoCs is proving to be challenging due to complex interactions among various subcomponents and IPs, with multiple clock domains and diverse bus protocols. The quality of verification depends on the precision in specifying the interaction behaviors. We propose a visual specification language called CESC (Clocked Event Sequence Chart), designed to specify interaction scenarios in SoCs. CESC provides a unique mechanism for representating multiple clock domains, based upon which event occurrences and interactions among different subcomponents can be represented. CESC has a pictorial and textual syntax, and a formal semantics to enable rigorous analysis. The semantics is based on standard notions of partial ordering and timed event traces. CESC is useful in many ways in formalizing SoC verification flows, namely, formalization of verification scenarios, synthesis of protocol checkers and consistency checking of specification versus implementation. This paper describes an algorithm to translate CESC scenarios to protocol checkers used in SoC verification flow. A few examples from industrial designs are included to illustrate the applicability of this formalism in specifying bus transactions and properties of protocols.

The design and integration challenges for SOCs include DFT for test integration to meet the test quality and test cost goals. This work describes the DFT implementation on TNETD7300, a single chip ADSL modem SOC with analog and digital sub-systems, IP cores and embedded memories, to address several test optimisation requirements, including scan architecture support for high-end and low-cost testers, concurrent test of digital logic with analog functions, at-speed testing for logic operating in different clock domains and clock frequencies, testing non-homogeneous IP cores together, configurable memory BIST operation, static and dynamic burn-in, and a comprehensive set of SOC test modes to support these operations. These techniques have significantly influenced the silicon test of this device, and have also influenced the design and test methodology adopted in other similar designs in Texas Instruments.

While the topics of periodic and concurrent testing have been well researched in the literature, and techniques developed and deployed in mission critical systems for several years, the need for incorporating these techniques into nanometer technology chips is being felt now. Contrary to common belief, the need for periodic testing may exist even today and we may be missing failures during normal operation in dense chips. This panel debates on the need for periodically testing critical components of today's complex chips during in-use conditions in the field, and investigates the possible incompleteness of manufacturing time (one time) testing. Nanometer technology designs face the dual problems of design correctness upon manufacture as well as after it. Issues in the former are better understood and solutions have been proposed based on design styles and design margins, and accompanying design automation. However, issues in the latter are only analysed for reliability, as against for errors due to hard or soft failures, which require periodic testing in the field itself. This problem is aggravated as design geometries shrink, with an increasingly larger mis-correlation between the expected behaviour in simulation and the actual behaviour in silicon, and the increased susceptibility of designs to internal disturbances, (e.g. switching conditions), and external disturbances, (e.g. atmospheric radiation), resulting in an increasingly larger probability of incorrect operation during normal operation. Periodic testing in the field, in the form of test support built into the hardware system, has been employed in systems used in critical applications, e.g. mainframes in online transaction processing, process control systems, navigation control systems (including those used for spacecrafts), telephone exchanges, life saving equipment, high end test equipment, etc., where the operation must be uninterrupted and the tolerance to any error is nil. This panel will investigate the necessity of such forms of testing, (either concurrently with normal operation or at regular intervals), in a wider class of circuit functions built into today's complex chips, and sensitise the design and test community to this new challenge. The issues to be investigated include: (a) Reliability of today's chips on the field. Failure rates. Debug mechanisms presently in use. (b) Failure modes in nanometer technology designs during manufacturing and during use. Their impact on logic and memories. Impact of corresponding fault condition detection mechanisms on yield and reliability. (c) Adequacy of present defect screening techniques based on static test coverage. Enhancements to address very low DPPM (defective parts per million) requirements. Tradeoffs with design margins. (d) Circuit design and synthesis techniques for periodic testing. Design methodology changes required to support them. Type of faults targetted by them. (e) System level techniques for periodic testing. Design and integration of test IPs. Their re-use and applications.

The use of embedded cores poses several new problems in testing systems built around them. An important one amongst them is the need to achieve high fault coverage in an embedded context. Several impediments exist to obtaining a high fault coverage in such embedded systems. This paper presents a set of techniques for enhancing the fault coverage in an embedded DSP core based system. Its main contributions are: (i) examines the various test constraints in such a system and the impediments to achieving a high fault coverage therein; (ii) presents the development of functional testing techniques to enhance the coverage of the individual components; (iii) complements this effort by presenting fault analysis techniques, to further enhance this coverage. The techniques described in the paper have been used to improve the fault coverage of devices built around Texas Instruments new DSP core, TMS320C27xx. Results indicate the effectiveness of functional testing and fault analysis techniques in raising the DSP core and memory wrapper logic coverage above 95%, over and above the best results obtained through ATPG.

Intellectual property cores are being widely used to enable rapid integration of entire systems onto chips. While allowing for rapid system prototyping and design, this methodology complicates the problem of testing them. Various design for test techniques and guidelines are evolving across design groups for embedded core based systems. This paper discusses a framework: for evaluating these techniques and the tradeoffs therein, to drive a cost effective test methodology. Its main contributions include: (i) it inspects various techniques to improve the test coverage and test quality in embedded core based systems. (ii) It explains important test cost measures, and proposes a framework for making design time decisions to minimise the cost. (iii) It presents the results of various experiments carried out on representative DSP core based systems, built around Texas Instruments' new DSP core, TMS320C27xx. These results have highlighted various design, and test tradeoffs, and are being profitably used to drive a cost effective test methodology on newer cores and devices.

This paper presents a new test pattern generation technique for complex systems. It focusses on test vector propagation through the individual blocks in the system. The technique is based on an easy identification of input-output pairs in each block. E (equality)-groups are formed for each block such that all the input vectors producing an identical output are grouped together. Such a grouping speeds up the task of backward propagation. In contrast to earlier methods, which considered the circuit structure for propagation, this method uses a functional approach and propagates the entire vector in one step. It is especially relevant to systems which consist of several blocks through which the test vector must be propagated. Results show that a significant reduction in the test generation time is possible.