Heating ventilation and air conditioning (HVAC) drives utilize variable speed control to maximize efficiency. Power factor correction (PFC) stage is used in the rectifier design in these applications to comply with regulations, such as IEC 61000-3-2, which limit the input current harmonics. Typically control of PFC and the motor stage is kept separate, due to limited CPU bandwidth, where fast is desired for PFC stage (up to 200 kHz) and motor inverter (10-20 kHz). This paper presents a MCU with control law accelerator (CLA) architecture, which enables integration of dual motor control and PFC on a single controller, for a cost sensitive application such as HVAC. In addition to cost reduction and performance improvement, the integration enables the control of the stages together. Also, the surplus bandwidth provided by the CLA, allows the execution of slow background tasks, diagnostics and communication. Integration challenges with software and system level details for the proposed solutions are highlighted in the paper. Additionally improvements to the PFC algorithm using a nonlinear control technique for better output voltage control under dynamic load conditions are presented.

Long distance, low data-rate UWB communication for sensor network applications requires a highly energy efficient transceiver combined with circuit and system-level optimizations to maximize range. A custom pulsed-UWB transceiver chipset in 90 nm CMOS is presented that targets these aggressive specifications. The transceiver efficiently communicates at data rates from 0-to-16.7 Mbps in three 550 MHz-wide channels in the 3.1 to 5 GHz band by using pulse position modulation (PPM). The transmitter uses an all-digital architecture and calibration technique to synthesize pulses with programmable width and center frequency. The non-coherent receiver operates at 0.65 V and performs channel selection Altering, energy detection, and bit-slicing. As FCC regulations limit the maximum transmit power of UWB communication, a run-length limiting technique is presented to reduce energy requirements when maximizing range at low data rates.

This paper describes how parallelism in the digital baseband processor can reduce the energy required to receive ultra-wideband (UWB) packets. The supply voltage of the digital baseband is lowered so that the correlator operates near its minimum energy point resulting in a 68% energy reduction across the entire baseband. This optimum supply voltage occurs below the threshold voltage, placing the circuit in the sub-threshold region. The correlator and the rest of the baseband must be parallelized to maintain throughput at this reduced voltage. While sub-threshold operation is traditionally used for low energy, low frequency applications such as wrist-watches, this paper examines how sub-threshold operation can be applied to low energy, high performance applications. The correlators are further parallelized for a 31x reduction in the synchronization time, which along with duty-cycling, lowers the energy per packet by 43% for a 500 byte packet. Simulation results for a 100 Mbps UWB baseband processor are described

A key challenge in ad-hoc, data-gathering, wireless sensor networks is achieving a lifetime of several years using nodes that carry merely hundreds of joules of stored energy. We explore the fundamental limits of energy-efficient collaborative data-gathering by deriving upper bounds on the lifetime of increasingly sophisticated sensor networks.

We ask a fundamental question concerning the limits of energy efficiency of sensor networks-what is the upper bound on the lifetime of a sensor network that collects data from a specified region using a certain number of energy-constrained nodes? The answer to this question is valuable for two main reasons. First, it allows calibration of real world data-gathering protocols and an understanding of factors that prevent these protocols from approaching fundamental limits. Secondly, the dependence of lifetime on factors like the region of observation, the source behavior within that region, basestation location, number of nodes, radio path loss characteristics, efficiency of node electronics and the energy available on a node, is exposed. This allows architects of sensor networks to focus on factors that have the greatest potential impact on network lifetime. By employing a combination of theory and extensive simulations of constructed networks, we show that in all data gathering scenarios presented, there exist networks which achieve lifetimes equal to or >95% of the derived bounds. Hence, depending on the scenario, our bounds are either tight or near-tight.

An increasingly important figure-of-merit of a VLSI system is "power awareness," which is its ability to scale power consumption in response to changing operating conditions. These changes might be brought about by the time-varying nature of inputs, desired output quality, or just environmental conditions. Regardless of whether they were engineered for being power aware, systems display variations in power consumption as conditions change. This implies, by the definition above, that all systems are naturally power aware to some extent. However, one would expect that some systems are "more" power aware than others. Equivalently, we should be able to re-engineer systems to increase their power awareness. In this paper, we attempt to quantitatively define power awareness and how such awareness can be enhanced using a systematic technique. We illustrate this technique by applying it to VLSI systems at several levels of the system hierarchy - multipliers, register files, digital filters, dynamic voltage-scaled processors, and data-gathering wireless networks. It is seen that, as a result, the power awareness of these preceding systems can be significantly enhanced leading to increases in battery lifetimes in the range of 60-200%.

The Residue Number System (RNS) offers unlimited opportunities for high performance arithmetic provided efficient forward and reverse converters could be constructed for the moduli set at hand. All forward conversion proposals to date, require some form of Read Only Memory (ROM) along with computational elements like Full Adders (FA). In this paper, we show that by formulating the forward conversion problem in terms of modular exponentiation and addition, we can achieve memory free conversion. We generalize our solution such that bit serial and bit parallel implementations can be derived by simply varying a parameter, namely, multiplexers. Apart from this formulation itself, the paper makes two other contributions. Firstly, it demonstrates an entirely new set of converters that use no look up. Secondly, we show how conversion complexity can be reduced significantly by sharing circuitry over several forward converters.

The authors propose an extension to the popular {2/sup n/-1, 2/sup n/, 2/sup n/+1} moduli set by adding a fourth modulus "2/sup n+1/+1. This extension leads to higher parallelism while keeping the forward conversion and modular arithmetic units simple. The main challenge of efficient reverse conversion is met by three techniques described for the first time. Firstly, we reverse convert linear combinations of moduli hence reducing the number of non-zero bits in the Booth encoded multiplicands from n to merely 2. Secondly, it is shown that division by 3, if introduced at the right stage, can be implemented very efficiently and can, in turn, reduce the cost of the converter. To implement VLSI efficient modulo reduction, we propose two techniques-multiple split tables (MST) and a modified division algorithm (MDA). It is shown that the MST can reduce exponential ROM requirements to quadratic ROM requirements while the MDA can reduce these further to linear requirements. As a result of these innovations, the proposed reverse converter uses simple shift and add operations and needs a lookup with only 6 entries. The delay of the converter is approximately 10n+13 full adder delays and the area cost is quadratic in n.

This paper reports how VLSI cost metrics (area, delay, power) of residue reverse converters scale with the cardinality and dynamic range of moduli sets. The study uses CMAC reverse converters, reported previously by the authors to be the most efficient known to date in terms of area and delay. In all, 134 reverse converters with dynamic ranges from 32 to 120 bits and set cardinalities ranging from 4 to 20 are actually constructed and analyzed. It is seen that area, delay and power costs are cardinality insensitive once the cardinality exceeds a threshold (usually between five to eight). For cardinalities beyond this threshold, conversion costs are essentially dynamic range dependent. This insensitivity is explained in detail by noting the counterbalancing effects of the various sub-units of a CMAC reverse converter. Since practical implementations of RNS usually employ cardinalities beyond the abovementioned thresholds, the significance of this study is its conclusion that increasing the set cardinality in most implementations will have a marginal, if any, effect on VLSI reverse conversion costs.

Recent trends like increasing operating frequencies, larger die sizes and demand for greater portability make power reduction a hard taskmaster. It is acknowledged that the greatest returns come from optimization at the architectural and technology level. We present, for the first time, residue architectures that reduce the power by more than 70% without changes in technology. This reduction is achieved without sacrificing performance and with minimal sacrifice in area (less than 60%). The key to such low power solutions is trading-off the speed gained by parallelism for lower power. Existing proposals that achieve similar trade-offs demand an area increase of more than a factor of two and also increased control complexity. Other benefits of using residue arithmetic for low power is the significant reduction in peak current and increased design locality. The role of the number of computations per forward (or reverse) conversion in determining the power characteristics of the system are also analyzed and explained. The effectiveness of the methodology is illustrated using a system that extracts a 256-point FFT of the input signal.

The most important reason for the lack of commercial residue arithmetic (RA) based systems is not the "slow" and area consuming reverse conversion, but the absence of research that explores the system-level trade-offs of such arithmetic in actual VLSI implementations. Such system-level issues are-choice of the moduli set, effect of moduli imbalance on resulting VLSI implementation, choice of the reverse and forward convertors, use of lookup versus computation for modular operations, system characteristics that indicate RA suitability and finally, typical VLSI area and performance figures. This paper explains these concerns by presenting novel RA architectures for VLSI correlators employed in radioastronomy and ultrasonic blood flow measurement. A state-of-the-art, high performance (80-100 MHz), RA-based correlator ASIC was successfully fabricated as a result of this research.