Recent demand and initiatives in brain research have driven significant interest toward developing chronically implantable neural interface systems with high spatiotemporal resolution and spatial coverage extending to the whole brain. Electroencephalography-based systems are noninvasive and cost efficient in monitoring neural activity across the brain, but suffer from fundamental limitations in spatiotemporal resolution. On the other hand, neural spike and local field potential (LFP) monitoring with penetrating electrodes offer higher resolution, but are highly invasive and inadequate for long-term use in humans due to unreliability in long-term data recording and risk for infection and inflammation. Alternatively, electrocorticography (ECoG) promises a minimally invasive, chronically implantable neural interface with resolution and spatial coverage capabilities that, with future technology scaling, may meet the needs of recently proposed brain initiatives. In this paper, we discuss the challenges and state-of-the-art technologies that are enabling next-generation fully implantable high-density ECoG interfaces, including details on electrodes, data acquisition front-ends, stimulation drivers, and circuits and antennas for wireless communications and power delivery. Along with state-of-the-art implantable ECoG interface systems, we introduce a modular ECoG system concept based on a fully encapsulated neural interfacing acquisition chip (ENIAC). Multiple ENIACs can be placed across the cortical surface, enabling dense coverage over wide area with high spatiotemporal resolution. The circuit and system level details of ENIAC are presented, along with measurement results.

We present a hierarchical address-event routing (HiAER) architecture for scalable communication of neural and synaptic spike events between neuromorphic processors, implemented with five Xilinx Spartan-6 field-programmable gate arrays and four custom analog neuromophic integrated circuits serving 262k neurons and 262M synapses. The architecture extends the single-bus address-event representation protocol to a hierarchy of multiple nested buses, routing events across increasing scales of spatial distance. The HiAER protocol provides individually programmable axonal delay in addition to strength for each synapse, lending itself toward biologically plausible neural network architectures, and scales across a range of hierarchies suitable for multichip and multiboard systems in reconfigurable large-scale neuromorphic systems. We show approximately linear scaling of net global synaptic event throughput with number of routing nodes in the network, at $3.6\times 10^{7}$ synaptic events per second per 16k-neuron node in the hierarchy.

Recent advances in neuromorphic engineering for brain-like computing and neural prostheses are converging towards realization of electronic synaptic arrays approaching the integration density and energy efficiency of the human brain. A major impediment in this development is the real-time synaptic routing in a large-scale spiking neuron architecture. Here we present a hierarchical address-event routing (HiAER) communication architecture for routing neural events in a scaleable reconfigurable large-scale neuromorphic system. The neural events are routed in real-time through synaptic connections with configurable parameters governing connectivity, synaptic strength, and axonal delay. The HiAER architecture is implemented on a hardware platform with five Xilinx Spartan-6 FPGA cores.

A digitally controlled resonant tank oscillator with loop antenna radiating inductor offers high energy efficiency in BFSK transmission, however suffers from frequency drift. Here we present a fast-settling adaptive digital architecture for dual-loop frequency locking of a BFSK transmitter. The method uses interleaved frequency-locked loops (FLL) that allow fast and energy-efficient direct digitally controlled oscillator (DCO) frequency modulation at a data rate exceeding the settling time of the frequency adaptation, while maintaining frequency regulation. The fully digital FLL architecture retains the dual-loop adapted states between transmission bursts, allowing for energy efficient low duty cycle transmissions with minimal or no settling transient at the beginning of a transmission burst. Analysis and simulation results are presented of the architecture operating in the 402-405 MHz MICS band for biomedical applications, indicating locking at 130 kHz frequency resolution at 115 μs settling for 125 kbps BFSK telemetry.

We present an automatic method to produce compact equivalent circuit models of spatially inhomogeneous resistors. Local variations in space of the resistivity due to physical interactions such as magnetic fields or mechanical stress are automatically included. The equivalent circuit model is computed using symbolic algebra, such that the functional relation between the resistivity and the fields interacting with it is included in the circuit design model. Modeling is based on the discretization of the sensor geometry with a mesh of elements and vertex nodes together with the current continuity equation using the box integration method. The resistivity is described by the tensor field of electrical conductivity and depends on the physical interactions to be modeled. The element internode conductivity is mapped to a set of lumped conductances and transconductances (voltage controlled current sources) between the nodes of the discretization mesh. These conductances and transconductances are translated into an equivalent circuit net list. Optionally, the electrical network representing the sensor is simplified before translation by symbolic linear algebra. Thus, equivalent circuit models consisting of many simple elements can be generated as well as models with only a few, algebraically complicated elements. The method is demonstrated using the public domain circuit simulator SPICE3 for the example of a magnetic Hall sensor, with and without the piezoresistive effect.