Effect-Cause diagnosis procedures are used to diagnose failing dies and improve manufacturing yield. Several methods have been proposed to accelerate Effect-Cause diagnosis procedures by utilizing a small-sized fault signature dictionary. Recently, pre-silicon diagnosis simulation has been proposed to identify quality issues in diagnosis before silicon volume production. Asymmetric Partition Trees (APT) have been proposed to extract useful information in the fault dictionary for diagnosis simulation applications. APT has proven to have a minimum tree size. In this paper, we propose using fault group information in APT to distribute the fault signature dictionary across APT tree nodes. With APT, the small fault signature dictionary can be further reduced, thereby improving diagnosis performance. The larger the designs, the greater the savings.

Diagnosis simulation based on stuck-at faults cannot expose all chain diagnosis problems because silicon defects don’t behave exactly as stuck-at faults. For chain failures, the fault effect can be activated during scan shift cycles and capture cycles in scan test patterns. The activation conditions of silicon defects are generally more complex and do not activate the fault effect in all cycles. To accurately estimate diagnosis coverage during chain diagnosis simulation, this paper proposes using distinguishing bits. Distinguishing bits, which are simulation-failing bits of one fault but not simulation-failing bits of another fault, are used in this paper to distinguish each silicon defect from others. The chain diagnosis quality of silicon defects can be improved by increasing the distinguishing bits of all scan cell faults. Specific diagnosis test patterns are proposed to increase the number of distinguishing bits of each fault. If the diagnosis test patterns cannot be created, adaptive diagnosis points are proposed to modify the designs to facilitate the creation of these diagnosis test patterns.

Performing scan test failure diagnosis is necessary for advanced semiconductor manufacturing technologies to improve yield. A pre-silicon diagnosis simulation is essential to avoid low diagnosis resolution during volume production. Like fault simulation to identify test quality problems, diagnosis simulation identifies diagnosis quality problems. The issues can be classified into three areas: (1) Failing data collected from the automatic test equipment (ATE) is insufficient for diagnosis. To fix this problem, ATE needs to use larger fail data storage; (2) Production scan test patterns are not adequate for diagnosis, such that better test pattern selection or new diagnosis-specific test patterns should be used; (3) Designs are not friendly for diagnosis, so design-for-diagnosis enhancements should be used.A fault dictionary with complete failing bit information on all faults can be used for diagnosis simulation. However, a fault dictionary requires lots of memory to store the failing bits and a long time to query the dictionary. We propose using an Asymmetric Partition Tree (APT) to extract the information stored in a fault dictionary for diagnosis simulation usage. APT can be used to calculate diagnosis coverage and analyze the impact of ATE failed data storage limit on diagnosis coverage with and without ATE pin-based storage limit. The information stored in APT also benefits other applications, such as diagnosis pattern sampling. APT can be proven to have the minimum tree size for diagnosis simulation.

Advancements in integrated circuit manufacturing technology and design complexity have been accompanied by challenges in efficiently ensuring product quality. Aggressive product usage scenarios in critical market segments, such as data centers and automotive, necessitate management of products throughout their lifetime ensuring graceful degradation and replacement. In this session, our first two presenters will discuss defect diagnosis methodologies to enhance product yield and manufacturing quality, while the final presenter will discuss methods to track and address in-field issues.

A pre-silicon design-for-diagnosis flow is a critical step in IC manufacturing. It is the key to achieving high diagnosis quality, which is necessary to improve yield and meet time-to-volume business requirements. This paper introduces a novel mechanism that significantly enhances this process. By inserting an XOR gate at scan cells, we enable these cells to operate in an additional mode, thereby improving their diagnosability. The activation of this extra mode is facilitated by a combination of a diagnosis-enable signal bit and the scan-enable signal. A key aspect of our approach is using a local scan cell without an additional input pin to provide the diagnosis-enable signal, a practical innovation that enhances the efficiency of the manufacturing process.

Reversible scan chain is an architecture targeted towards improving the quality of chain diagnosis. In this scan architecture, chains are designed to shift the test data in both directions to isolate a defect. We implemented this technique on a test chip in one of the most advanced technology nodes to measure its benefit over its cost. Test chips are typically low in volume and may suffer from worse diagnosis resolution and lower diagnosis convergence than production chips due to early process technology. Hence, it is very important to enhance diagnosis resolution and increase successful diagnosis data volume without losing accuracy to help expedite yield learning. In this paper, the detailed evaluation method together with silicon data and failure analysis results are presented. Moreover, we utilize this novel methodology for improving diagnostics suspect resolution and physical area. Overall, we observe significant benefit in diagnosis quality. Specifically, 4X improvement in the number of suspects and up to 7X improvement in suspect cell area is observed without losing accuracy. Design overhead is also presented and discussed.

Test cost has become a critical issue for large industrial integrated circuits. Various test compression techniques have been adopted in the industry to reduce test cost. However, appropriate input and output channel counts must be selected to utilize the test compression technology best. This paper presents an efficient and effective method to estimate the test pattern counts under different compression configurations for the Embedded Deterministic Test (EDT) compression technique. In searching for the accurate estimation method, we build mathematical models that reveal the internal relationship among different compression configurations. The models are established based on novel theoretical analysis as well as actual experimental data. Accurate estimation of test pattern counts for a wide range of compression configurations can be obtained based on the results of only two ATPG runs. Experimental results on nine industrial circuits show that the average error rate of pattern count estimation is about 5%, with very few outliers. With the proposed method, a test compression designer can easily pick the best input and output channel configuration to fit the design needs.

Test costs for large industrial designs increase rapidly in recent years. On-chip test compression hardware has become a pragmatic technology to cut down the overall test costs by reducing the test data volume. Determining the input and output channel counts of test compression hardware that results in minimum test data volume is thus a critical issue. In this article, efficient methods to estimate test pattern counts for an extensive range of input/output counts are developed. These methods require only a small number of ATPG runs. The estimation results can then be utilized to determine the test data volume for each input/output configuration. The configuration with the estimated lowest test data volume thus can be determined. The pattern count results of each configuration for a design can also be used to determine the best suitable configuration when the design is to be embedded in an SoC system.

As the manufactural technologies are moving to deep sub-micron process, the defects inside the design library cells occur more often during manufacture. Cell-Aware Testing (CAT) had been proposed to improve the test quality on detecting the cell internal defects. In CAT, the analog simulator is used to simulate the cell input combinations exhaustively for every defect to identify all the cell input combinations that detect the defects in the cells. However, it becomes less practical to handle the complex cells with large number of inputs and to consider multiple capture cycles because of the computational complexity of the analog simulation when processing the extremely large number of the input combinations. In this paper, we propose to model the design library cells as the ATPG library cells at the transistor level such that the existing ATPG tools can be used to generate the exhaustive test sets for every cell internal defect more efficiently. The generated test patterns are further divided into the hard-detection set and the soft-detection set. Only the test patterns from the soft-detection set need to be simulated by the analog simulator to verify the capability and the confidence level on detecting the defect. Using the proposed method can dramatically speed up the time-consuming step in the CAT flow, that is, for every defect to identify all input combinations that detect the defect through the analog simulation.

With the advanced technology used in the semiconductor manufacture process, systematic defects related to layout patterns and litho process are the major cause of yield issues. In this industry session, we invite three experts from three EDA companies to share their experiences of diagnosis and yield learning.

A novel method to efficiently and accurately prognosticate the pattern count at different input compression ratios with the Embedded Deterministic Test (EDT) compression technology is proposed. With this method the total ATPG run time can be significantly reduced compared to the currently used trial-and-error method.

GPGPU, general-purpose computing on graphics processing units, has been witnessed growing from a niche to a mainstream computing paradigm in the last decade. It is widely deployed in machine learning, artificial intelligence, and many scientific applications. In this article, we study gate-level logic simulation for scan test patterns, one of the key algorithmic components for test generation, fault grading and design rule check. We are exploring if GPGPU can deliver scalable performance speedup as promised by its massive parallelism. We discuss the limitations of the state of art work. With GPUs' architectural features in mind, a novel algorithm of hybrid race-tolerant parallel logic simulation is proposed to unleash its immense power of parallelization. Its unique integration of oblivious simulation and event-driven simulation leads to a scalable realization of parallel logic simulation for scan patterns. For the first time in the literature, it is demonstrated that a modest GPU can handle an industrial design of over twenty million gates with excellent performance scalability.

Over the past two decades, test data compression has become a de facto technology used in large industrial designs to reduce the overall test cost. During DFT planning, it is very important to understand the impact of using different numbers of input/output channels on test coverage, test cycles, and test data volume. In this paper, an efficient method to estimate the test data volume with different input channel counts using the Embedded Deterministic Test (EDT) compression technology is proposed. The results can then be used to quickly determine the scan configuration that results in the least or near least test data volume. With this method, the total ATPG run time can be reduced by a factor of more than 10X compared to the currently used trial-and-error method.

As the complexity of industrial integrated circuits continue to increase rapidly, test data compression has now become a de facto technology for large designs to reduce the overall test cost. During the design for test (DFT) planning, it is critical to understand the impact of using different numbers of input/output test channels on test coverage, test cycles, and test data volume. In this paper, two approaches to predict the test pattern counts and test data volumes with different input channel counts are presented, one with the compression tool able to generate channel-scaling patterns and the other without this capability. The results can be used to determine the scan test configuration that results in the smallest or near smallest test data volume. Experiments on industrial circuits show that the average error rates of pattern count prediction for most circuits are less than 10% for both approaches. The error rates of the predicted smallest data volumes are all less than 3.5%. The total ATPG run time can be reduced by a factor of more than 10X compared to the currently used trial-and-error approach.

Diagnosis of intermittent scan chain failures still remains a hard problem. In this article, we demonstrate that the use of artificial neural networks (ANNs) can lead to significantly higher accuracy. The key of this method is a multistage process incorporating ANNs with gradually refined focuses. During this process, the final fault suspect is elected through multiple rounds of ANN inference, instead of just one round. At each stage, identification of a proper Affine Group, used as the “candidate set of scan cells for the next round of ANN inference,” will influence the final diagnostic accuracy. Thus, we propose a validation-based learning procedure for Affine Group derivation to further boost the final diagnostic accuracy. The experimental results on benchmark circuits have shown that this method is, on the average, 17.46% more accurate than a state-of-the-art commercial tool for intermittent stuck-at-0 faults.

Diagnosis of intermittent scan chain failures remains a hard problem. We demonstrate that Artificial Neural Networks (ANNs) can be used to achieve significantly higher accuracy. The key is to take on domain knowledge and use a multi-stage process incorporating ANNs with gradually refined focuses. Experimental results on benchmark circuits show that this method is, on average, 20% more accurate than a state-of-the-art commercial tool for intermittent stuck-at faults, and improves the hit rate from 25.3% to 73.9% for some test-case.

Timing exceptions are commonly used to indicate that the timing of certain paths have been relaxed so as to enable the design to meet timing closure. Generating scan-based test patterns without considering timing exceptions can lead to invalid test responses, resulting in unpredictable test quality impact. The existing simulation-based solution masks out unreliable signals after a test pattern is generated. If the signals required for detecting the target fault are unreliable and masked out, the generated test pattern fails to detect the target fault, and it is discarded. To achieve an acceptable test coverage, several iterations of test generation with a randomized decision-making process are typically required where different tests are generated for target faults. In this paper, an innovative deterministic ATPG algorithm called TEA (Timing Exception ATPG) is proposed to prevent the generated test patterns from being impacted by timing exceptions. The deterministic algorithm is compatible with the existing simulation-based approach. In this simulation environment, TEA is complete such that for a target fault, the test pattern generated is guaranteed to detect it. If a test pattern cannot be generated using TEA, the target fault is untestable given the timing exception paths in the design and the existing simulation environment. Compared to the existing simulation-based approach, using TEA can generate a more effective test set, improving test coverage, test pattern count, and the total ATPG run time significantly.

With the increase in design complexity and test data volume, compressed tests together with on-chip test decompression hardware such as Embedded Deterministic Test (EDTTM) are widely used in industry in order to reduce test cost. One of the challenges of such Design-for-Test (DFT) technology is to determine a set of optimal parameters such as the number of scan chains, scan channels, power budget, etc. such that it can reach the highest test coverage with a minimum amount of test data volume whilst satisfying various other constraints. To achieve the optimal compression configuration quickly, in this work deep learning technology based on Tensorflow is explored to estimate the test coverage and the data volume for a design when employing EDT under a given set of circuit parameters. Based on the estimated data, the optimal test architecture is also predicted, yielding a more efficient approach compared to the currently used trial-and-error methods. To demonstrate the advantages of our deep learning approach over the currently used utility, we present experimental data for eight industrial designs.

Volume diagnosis has been used effectively to identify systematic defects for yield learning. Root cause deconvolution (RCD), an unsupervised machine learning technique which uses volume diagnosis data, has proven very effective for identifying root causes. As we march towards more advanced technology nodes, defects have more complicated behaviors rendering some model parameters used in RCD are not precise enough to be effective. In this paper we use a supervised machine learning technique to accurately learn these model parameters from training data. Controlled experiments using simulation data on several industrial designs show that our approach improves RCD accuracy. We also demonstrate that the approach correctly predicts 71% of the systematic defects in 21 cases validated by physical failure analysis of real silicon, which is a significantly better result compared to using the original parameters.

The semiconductor industry ramping up design capabilities for emerging technologies is facing unprecedented test quality and yield management challenges. To facilitate diagnosis of yield issues and to enable repair processes, an accurate defect isolation is needed with support of more advanced test, diagnostic, and yield analysis tools. Scan remains instrumental in developing more advanced DFT technologies, including logic BIST and on-chip test data compression. Its reliable operations are essential for test pattern bring-up, failure analysis, and yield learning. This paper demonstrates how to re-architect on-chip test data compression environment to enable multiple and repeated scan integrity tests for advanced test procedures, including various forms of stroboscopic electron-beam imaging and laser voltage imaging. The presented approach avoids the repetitive loading of scan chains and therefore reduces significantly test time and may support advanced diagnostic techniques. The new solution has virtually no area overhead, and does not compromise the performance of the original test logic.

A clock network is not only difficult to design, but also challenging to test. For high-performance designs with a rigorous clock-skew requirement, small defects in a clock tree network could lead to unexpected failures in the field and thus need to be identified during the manufacturing test. In this paper, we present a novel flush test procedure to determine if a clock network has any small delay faults. This method does not require any change of the clock network, but it does require a “special test clock signal,” which can be generated on the chip by using only standard cells. Experimental results of transistor-level simulation on benchmark circuits injected with resistive open defects in the layout show that the proposed method is capable of detecting a delay fault as small as 52.8 ps.

in many cases, the main cause of yield loss is a specific layout pattern that is difficult to manufacture and is prone to causing an open or short defect. This situation is getting worse with advanced technology nodes due to small feature sizes and complex manufacturing processes. Volume scan diagnosis results are a rich data source for identifying such yield limiting layout patterns, but a big challenge is how to deal with an enormously large number of potential layout patterns to be considered for analysis and how to avoid over fitting. In this paper we present enhancements to the previously published root cause deconvolution technique for analyzing volume scan diagnosis data that enables it to overcome this and correctly, and automatically, determine the right layout patterns causing systematic yield loss. Also presented is an application to industrial data where a layout pattern identified by the new technique was validated by physical root cause analysis to be the dominant yield loss mechanism.

Scan-based testing has proven to be a cost-effective method for achieving good test coverage in digital circuits. It was reported in prior papers that about 30% to 50% of all failing die were due to defects that cause scan chains to fail [1][2]. Therefore, scan chain failure diagnosis is very important to improve yield. The previously proposed methods of chain diagnosis were primarily based on either deterministic fault models and simulation algorithms or probabilistic analysis. To handle hard-to-model defect behaviors more robustly, in this paper, we propose a new scan chain diagnosis algorithm based on unsupervised machine learning. Its application on "scannable memory designs" (SMD) is demonstrated to illustrate the effectiveness of the proposed algorithm.

With decreasing feature sizes and increasing complexity of fabrication processes for manufacturing VLSI semiconductor devices, more systematic defects occur at the advanced technology nodes. Product yield ramp up is mostly determined by how fast systematic defects are identified and fixed. Given the long times and expense of physical failure analysis (PFA), use PFA on a large number of failing devices to find systematic defects is becoming infeasible. For this reason, volume diagnosis data mining for root cause identification based on statistical methods is used to reduce turnaround time and cost to speed up the process of systematic defect identification. The identified root cause information not only can be used to improve yield analysis but also can reduce PFA cost by focusing on failing devices with systematic defects.

Scan chain diagnosis plays an important role in silicon debug and yield ramp-up since 10% to 30% of chip failures are caused by scan chain failures. Failure data collected on testers is limited by buffer sizes to capture the failing responses from scan chains, especially since scan chain failures produce a large amount of failing responses. In this paper, we propose a new pattern selection method to maximize the chain diagnosis resolution when limited failure information is collected from the tester. Experimental results on industrial designs show our method achieves higher diagnosis resolution than previous method.

A clock network in a 3D-IC is not only difficult to design, but also challenging to test. For high-performance designs with a rigorous clock-skew requirement, studies have shown that small defects in a clock tree network could lead to unexpected failures in the field and thus need to be identified during the manufacturing test. In this paper, we present a novel test method to determine if a clock network has any small delay faults. This method does not require any change of the clock network, and it is capable of detecting a delay fault as small as 50ps through outlier analysis, while locating the FFs affected by the fault.

In today's multi-die ICs, the die-to-die interconnects are often complicated and susceptible to various kinds of manufacturing defects and stress-induced performance degradation in the field. This phenomenon has prompted a need to perform online monitoring of the signal integrity over the die-to-die interconnects for reliability critical applications. In this work, we present a slack-time binning scheme so that one can constantly quantify the margin of a timing failure threat (TFT) occurring to a registered die-to-die interconnect. The proposed scheme attaches a Slack-Time Monitor (ST-monitor) to each Flip-Flop (FF) that receives a signal transmitted through a die-to-die interconnect under monitoring. Two techniques are introduced to enhance the traditional “Timing-Violation Checker”, namely (1) a tunable guard-band technique, and (2) an offset compensation technique. With these two techniques, one can perform online slack-time binning. Experimental results using a 90nm CMOS process show that the proposed scheme has a low area overhead of only approximately 2.35 times the area of a boundary scan cell.

Detecting the defects inside the CMOS cells, especially the stuck-open faults, has gained a lot of attentions in recent years. It had been shown the test set generated by using the transition fault model is not sufficient to detect the stuck-open faults. In this paper, we propose an enhanced transition fault model, named cell transition, to improve the quality of the transition test set on detecting the stuck-open faults inside the CMOS cells. The fault sites targeted by the proposed model are placed at the cell boundary in order to keep the fault population similar to the transition fault model. Experimental results demonstrate the cell transition test set detects more stuck-open faults than the transition test set while the test coverage achieved for the transition faults is close to that obtained by the transition test set. Moreover, the number of generated tests is slightly higher than the transition test set.

In this paper, we surveyed the recent advancements in DDYA, which includes scan-based diagnosis technologies and diagnosis driven yields analysis. Multiple industrial cases studies are given to illustrate the values of the DDYA flow. By using the advanced DDYA, diagnosis can be more accurate, fast and informative. More importantly it can help improve yield by finding the systematic defect, identifying the root causes, correlating diagnosis results with DFM and picking highly possible die and suspect for PFA to validate all the findings.

Interconnects are sophisticated in a multi-die IC using integration technology such as interposer or Wafer-Level Packaging (WLP), and thus they could become vulnerable to early lifetime failure or aging. Our previous work in [12] provides a way to monitor the delay of a TSV non-intrusively by a transition time binning procedure. However, it is not suitable for longer interconnects in an interposer or in the Re-Distribution Layer (RDL) of a WLP-packaged IC, as the cost could become prohibitively high due to large area overhead. To overcome this limitation, we propose a new scheme in this paper by incorporating a Distributed Time-to-Digital Converter (d-TDC). Experimental results indicate that such a scheme can support on-line delay monitoring for long interconnects, while having an area overhead equivalent to 2 boundary scan cells only for each interconnect.

Die-to-die interconnects linking multiple functional dies in a modern 3-D or 2.5-D IC by micro-bumps could experience resistance increase after certain time of field operation due to parametric defects or aging. To cope with this reliability threat, we present an “on-line transition-time binning method” that aims to continuously detect excessive transition time occurring at a target die-to-die interconnect. Our method attaches a monitor to the termination end of each target interconnect. Any transition (rising or falling) is converted into a pulse-width first, which is then further compared to a dynamically tunable threshold for a binary pass/fail judgment. By multiple runs of transition-time monitoring while sweeping the threshold incrementally, the “transition-time bin” of each target interconnect can be derived and thereby a timing failure threat can be detected by a monitor center before it actually strikes.

A faulty interposer in a 2.5-D integrated circuit often results in a hefty loss as the potentially expensive known-good-dies bonded on the interposer will have to be discarded as well. To avoid such a last-minute loss during a multichip integration process, built-in self-repair (BISR) is highly valuable. Even though there have been many BISR schemes in the literature, the proposed method offers a number of distinct features. First, it can target not only catastrophic faults, but also timing faults. Second, it can be applied to general multi-pin interconnects and it can be applied to repair an interposer with multiple faulty interconnects. Third, it can perform the test-and-then-repair flow on-the-fly, and thereby eliminating the overhead of extra repair storage incurred in previous methods.

This paper presents several techniques employed to resolve problems surfacing when applying scan bandwidth management to large industrial multicore system-on-chip (SoC) designs with embedded test data compression. These designs pose significant challenges to the channel management scheme, flow, and tools. This paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with embedded deterministic test-based test data compression. The same solutions allow efficient handling of physical constraints in realistic applications. Finally, state-of-the-art SoC test scheduling algorithms are rearchitected accordingly by making provisions for: 1) setting up time-effective test configurations; 2) optimization of SoC pin partitions; 3) allocation of core-level channels based on scan data volume; and 4) more flexible core-wise usage of automatic test equipment channel resources. A detailed case study is illustrated herein with a variety of experiments allowing one to learn how to tradeoff different architectures and test-related factors.

Without appropriate stitching of scan chains, even with good diagnosis algorithm and diagnostic pattern generation, the chain diagnostic resolution may still be bad. In this paper, we propose a novel pattern-independent diagnosis and layout aware (DLA) scan chain stitching method: 1) the resolution is improved by increasing and properly distributing the sensitive scan cells, which can capture useful diagnostic information under both single- and multiple-fault situations; and 2) the scan cell layout placement is taken into account to reduce routing overhead and hence preserve the chip performance. Experiments using two different techniques to diagnose ISCAS'89/ITC'99 benchmark circuits with/without embedded scan compaction show the effectiveness of the proposed method in improving the diagnostic resolution. Impacts on chip performance, embedded scan compaction, transition fault coverage, and test power dissipation are negligible. The proposed method is also successfully applied to an industry circuit manufactured with 20-nm technology. The silicon results show 7× average resolution improvement comparing to without using the DLA scan chain stitching.

Through Silicon Vias (TSVs) are known to be susceptible to various thermal-mechanical and electro-migration effects that could lead to unexpected resistance increase after certain time of field operation. To cope with this reliability threat, we present an on-line monitoring method that aims to continuously detect excessive transition time occurring to a TSV (which often indicates performance degradation). Our method attaches a monitor to the termination end of a TSV. Any transition there is converted into a pulse-width, which is further compared to a dynamically tunable threshold. A Timing Failure Threat (TFT) is thereby detected when the pulse-width exceeds the threshold. This method can be applied to a large number of TSVs easily since the monitoring results are binary and can be stored in FFs forming a scan chain for easy access.

The industry is encountering an increasing number of front-end-of-line defects in the most advanced technology nodes due to extremely small feature size and complex manufacturing processes. Traditional scan diagnosis algorithms can locate a defective cell by examining its excitation conditions for cell internal defects, but cannot provide the more precise defect location inside the cell that is necessary for effective physical failure analysis and statistical yield learning. In this work, we propose a new cell-aware diagnosis algorithm, based on accurate fault models derived by analog simulation, that can pinpoint the defect location within a cell for various cell internal defects. The proposed method already has achieved dramatic resolution improvement for real silicon failures.

Interposer is a critical component in a 2.5-D IC as it serves as a common platform upon which multiple known good dies are bonded. Any defect in an interposer will lead to a loss of compound yield. To avoid such a last-minute yield loss, we propose a timing-aware Built-In Self-Repair method to increase the fault tolerance of high-speed interposer wires. The most unique feature of our method as compared to previous works is that ours can repair not only catastrophic faults, but also timing faults. We present an on-the-fly test-and-repair flow that can seamlessly link Pulse-Vanishing Test, a previous timing-aware interconnect test method, with a popular redundancy structure.

This paper addresses the testing and characterization of interposer wires in a 2.5-D stacked integrated circuit, which is essential for yield learning and silicon debug. The proposed method provides a number of distinctive features beyond previous works on interposer wire testing. First, we target not only catastrophic types of faults (such as stuck-at faults or hard bridging faults), but also parametric types of faults (including both resistive open faults and resistive bridging faults between interposer wires). Second, our method can also be used to characterize the propagation delay across each fault-free interposer wire.

In this paper, we present a general at-speed test method for die-to-die interconnects and demonstrate its particular application to the interposer wires in a 2.5-D IC. At the heart of this method is a pulse-vanishing test technique (called PV-test), in which a short-duration pulse signal is applied to an interposer wire under test at the driver end. If this pulse vanishes at the receiver's output, then it indicates the presence of a delay fault. This PV-test technique is effective for detecting not only resistive open faults, but also resistive bridging faults between interposer wires. This method has several other advantages. For example, the implementation is especially easy as it incorporates only logic cells and can be merged with boundary scan cells. Also, it can support on-the-spot diagnosis which is desirable in applications where subsequent built-in self-repair is needed.

Fault diagnosis plays an important role in physical failure analysis and yield learning process. With tens of billions of transistors being integrated in one chip, multiple faults may exist. With multiple faults, fault masking and reinforcing effects may appear. They may cause the conventional single-fault-based diagnosis methods such as the single location at a time (SLAT) to be invalid. The popular SLAT approach fails if there are not enough SLAT patterns that can be explained by a single stuck-at fault. Moreover, a real silicon defect may behave as different fault models (DM) under different failing patterns, which may invalidate the SLAT approach that uses a single-fault model across all failing patterns. In this paper, we introduce the concept of fault element to support multiple fault models, and use a fault-element graph (FEG) to consider fault masking and reinforcing effects among multiple faults. Based on the FEGs of all failing patterns, the most likely fault locations and their fault elements are iteratively identified. Meanwhile, the FEGs are iteratively pruned to keep track of the remaining multiple fault effects until all the fault locations are identified and all the FEGs are reduced to null. Experiments demonstrate that the proposed diagnosis method can identify the locations of multiple faults even under DM with high diagnostic accuracy and resolution.

Testing the quality of the interposer wires in a 2.5-D stacked IC can avoid the penalty arising from bonding known-good dies to a defective interposer. However, an interposer is particularly hard to test alone due to the lack of a device layer. This paper addresses this problem by proposing amid-bond test method - in which the interposer is tested after each die is attached to the substrate. We borrow the technique of pre-bond test method for the TSV and enhance it by a length-normalization scheme to cope with interposer wires of diverse wire lengths. Simulations show that this mid-bond test method can catch a high percentage of open faults before subsequent dies are attached.

Testing the speed of post-bond interposer wires in a 2.5-D stacked IC is essential for silicon debugging, yield learning, and even for fault tolerance. In this paper, we present a novel at-speed test technique called Pulse-Vanishing test (PV-test), in which a short-duration pulse signal is applied to an interposer wire under test at the d river end. If the pulse signal can successfully propagate through the interposer wire and reach the other end, then the interposer wire is considered fault-free. Otherwise, it indicates the presence of a delay fault. This new test technique has several technical merits. For example, the Design-for-Testability (DfT) circuit for an interposer wire is similar to the boundary scan cell and can be controlled through scan chain. Also, it can be easily adapted to perform at-speed Built-In Self-Test (BIST) supporting on-the-spot diagnosis.

Delay testing and characterization of interposer wires in a 2.5-D stacked IC is essential for yield learning and silicon debug. This paper addresses this problem by proposing a data analysis flow for perturbation-based oscillation test method to cope with the various wire-lengths of the interposer wires. With the proposed method, one can not only detect small delay faults but also characterize the delay across each fault-free interposer wire.

The paper discusses practical issues involved in applying scan bandwidth management to large industrial system-on-chip (SoC) designs deploying embedded test data compression. These designs pose significant challenges to the channel bandwidth management methodology itself, flow, and tools. The paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with EDT-based test data compression. Moreover, some recently proposed SoC test scheduling algorithms are refined accordingly by making provision for (1) setting up test configurations minimizing test time, (2) optimization of SoC pin allocation based on scan data volume, and (3) handling physical constraints in realistic applications. Detailed presentation of a case study is illustrated with a variety of experiments that allow one to learn how to tradeoff different architectures and test scheduling.

Without appropriate stitching of scan chains, even with good diagnosis algorithm and diagnostic pattern generation, it may still result in bad scan chain diagnostic resolution. To improve the diagnostic resolution, we propose a novel Diagnosis and Layout Aware (DLA) scan chain stitching method, which is pattern independent and supports embedded scan compaction. It is based on three ideas: (1) increasing the number of sensitive scan cells, which can capture useful diagnostic information; (2) properly distributing the sensitive scan cells along the scan chains to enhance the overall resolution; (3) stitching scan cells based on their placement at layout to preserve the chip performance. Experiments on ISCAS'89/ITC'99 benchmark circuits and a real industry circuit based on 20nm technology with silicon results show that, the proposed DLA scan chain stitching method effectively improves the resolution, with negligible impact on chip performance, embedded scan compaction, transition fault coverage, and test power dissipation. The silicon results even show 7X average resolution improvement comparing to without using the proposed method.

Diagnosis memory footprint for large designs is growing as design sizes grow such that the diagnosis throughput for given computational resources becomes a bottleneck in volume diagnosis. In this paper, we propose a scan chain diagnosis flow based on dynamic design partitioning and distributed diagnosis architecture that can improve the diagnosis throughput over one order of magnitude.

Testing the quality of prebond through-silicon vias (TSV) is a vital part of the Known-Good-Die test that is often necessary to retain a high compound yield for 3-D stacked integrated circuits. In this paper, we present a versatile prebond TSV test method applicable before wafer thinning when the deep end of the TSV is inaccessible as buried in the still-thick wafer. Technical merits include: 1) the ability to handle both the resistive open fault and the leakage fault in the same test structure; 2) a capability that allows an user to have a better measure of the severity of the fault; and 3) an all-digital and easy to implement design-for-testability circuit.

Leakage tests have been a challenge for through-silicon vias (TSVs) in a 3-D IC. Most existing methods are still inadequate in terms of the range of testable leakage currents. In this paper, we borrow the wisdom of the IO-pin leakage test while enhancing it with two features. First, we make it more suitable for a TSV, which has a much smaller capacitance than an IO pin. Second, we support a wide range of leakage test (e.g., from 0.125 μA to 16 μA), and thereby allowing for flexible test threshold setting and leakage characterization. To achieve this goal, we present two sets of techniques-1) wait-time generation by programmable delay line, and 2) wait-time propagation with a self-timed timing control scheme to overcome the timing skew problem due to signal routing. We demonstrate that the entire scheme can be done in only logic gates, making it easy to integrate into the common design flow.

A parametric delay fault could arise in a through-silicon via (TSV) of a 3-D IC due to a manufacturing defect. Identification of such a fault is essential for fault diagnosis, yield-learning, and/or reliability screening. In this paper, we present an innovative design-for-testability technique called variable output thresholding. We discovered that by dynamically switching the output of a TSV from a normal inverter to a Schmitt-Trigger inverter, the parametric delay fault on the TSV can be characterized and detected. SPICE simulation reveals that this technique remains effective even when there is significant process variation. A scalable test infrastructure indicates that the test time is modest at only 17.2 ms for 1024 TSVs and 648.8 ms for 32768 TSVs when the test clock is running at 10 MHz.

Summary form only given. Software-based diagnosis of scan test failures has been an established method for localizing defects as part of the failure analysis process for digital semiconductor devices. Diagnosis software determines the defect type and location for each failing device based on the design description, scan test patterns, and tester fail data. This gives failure analysis engineers or engineers involved in non-destructive testing and evaluation, a proven, and highly effective way of defect localization and identification, complementing their traditional, hardware-based failure analysis machine approach. Recent disruptions in yield enhancement capabilities such as dramatic increase in design sensitive defects and longer failure analysis cycle times have necessitated the development of new technology. As a result, better diagnosis, better failure data collection and better statistics method have been developed to analyze volume diagnosis data to provide value in a range of applications including technology yield ramp and product yield improvement. This tutorial describes how diagnosis-driven yield analysis (DDYA) accelerates time to root cause of yield loss and identifies yield limiters from volume diagnosis data. The underlying technology key to the methodology is an extremely accurate and consequential single-die diagnosis of scan test failures. Furthermore, specialized statistical analysis is used to identify and separate systematic yield limiters in seemingly random fail data and select the most suitable devices for failure analysis. The presentation will cover fundamentals as well as recent advances in diagnosis technology and diagnosis results analysis that drive the adoption of this approach:1) Layout-aware diagnosis provides detailed defect classifications that are significantly more valuable for yield analysis than defect locations alone.2) Scan chain diagnosis identifies and localizing defects in the test structures, scan chains themselves, simplifying a process that can otherwise be tedious and performed using dedicated and costly equipment.3) Novel machine learning techniques separate the noise that exists in diagnosis data to determine the underlying root causes represented in a population of failing devices from test data alone. This dramatically reduces the number of costly physical failure analysis to identify systematic defects. DFM analysis has significant impact to yield. A new approach will be explored to correlate DFM analysis and diagnosis results to identify DFM rules that most succinctly describe the design-process induced systematic defects.

In this paper we present a methodology to accurately diagnose cell internal defects when test patterns with multiple capture cycles are used. The multi-cycle test patterns can lead to more possible excitation conditions such that the existing extraction methods become less accurate. In addition, the realistic cell internal defects may produce different faulty values at different capture cycles, or only produce faulty values on some particular capture cycles. Thus the traditional logic diagnosis techniques may not accurately find the defective cells since most of them use stuck-at fault model to identify defect locations [1]. In the proposed methodology, we enhanced an excitation condition extraction procedure by back tracing from the observation points with fault effects during fault simulation to find the most possible input conditions that cause the fault effects. Additionally, a new method is proposed to locate defective cell locations without using stuck-at fault model. Experimental results on industrial designs proved the effectiveness of the proposed methodology.

Failure bitmaps of manufactured memory arrays may contain the information of some systematic defects and have hence been used to monitor the process and to improve the memory yield. It is important to have an accurate flow to classify the memory failure bitmap signatures. The memory bitmap signature classification can be either dictionary based or machine learning based. This paper introduces a hybrid flow that can combine dictionary based and machine learning based methods. The proposed method can enhance the accuracy of signature classification, and more importantly, it has the capability of learning new memory bitmap signatures unseen before.

Leakage test has been a challenge for TSVs in a 3D IC. Most existing methods are still inadequate in terms of the range of leakage currents they can test. In this work, we borrow the wisdom of the IO pin leakage test while enhancing it with two features: (1) we make it more suitable for TSVs which has a much smaller capacitance than an IO pin, and (2) we support leakage binning in a wide range of currents from 1 uA to 128 uA, and thereby allowing flexible test threshold settings and leakage characterization. Since we use only logic gates in the Design-for-Testability circuit, it is also easier to be integrated into the TSV design flow than previous methods.

In this work, we present a robust small delay test scheme for through-silicon vias (TSVs) in a 3D IC. By changing the output inverter's threshold of a TSV in a testable oscillation ring structure, we can approximate the propagation delay across that TSV, and thereby detecting a small delay fault. SPICE simulation reveals that this Variable Output Thresholding (VOT) technique is still effective even when there is significant process variation in detecting a slow TSV with some resistive open defect that may escape the traditional at-speed test.

A method based on dynamic design partition is presented to increase the throughput of volume diagnosis by increasing the number of failing dies diagnosed within a given time T using given constrained computational resources C. Recently we proposed a static design partitioning method to reduce the diagnosis memory footprint for large designs [1] to achieve this objective. The method in [1] is applied once for each design without using the information of test patterns and failure files, and then diagnosis is performed on an appropriate block(s) of the design partition for a failure file. Even though the memory footprint of diagnosis is reduced the diagnosis quality is impacted to unacceptable levels for some types of defects such as bridges. In this paper, we propose a new failure dependent design partitioning method to improve volume diagnosis throughput with a minimal impact on diagnosis quality. For each failure file, the proposed method first determines the small partition needed to diagnose this failure, and then performs the diagnosis on this partition instead of the complete design. Since the partition is far smaller, both the run time and the memory usage of diagnosis can be significantly reduced better than when earlier proposed static partition is used. Extensive experiments were conducted on several large industrial designs to validate the proposed method. It has been observed that the typical partition size for various defects is less than 3% of the size of the original design. Also diagnosis runs much faster (>;2X) on the partition. Combining these two factors, the throughput of volume diagnosis can be improved by an order of magnitude.

A TSV in a 3D IC could suffer from two major types of parametric faults — a resistive open fault, or a leakage fault. Dealing with these parametric faults (which do not destroy the functionality of a TSV completely but only degrade its quality or performance) is often trickier than dealing with a stuck-at fault. Previous works have not proposed a unified test structure and method that can characterize their respective effects. Based on our previous test structure, called VOT (Variable Output Threshold) scheme for delay faults, we propose a unified in-situ characterization flow for both parametric fault types of a post-bond TSV. With this flow, one can easily derive a more insightful assessment of a parametric fault in production test, process monitoring, and/or diagnosis-driven yield learning.

Recently statistical yield learning based on volume diagnosis has become popular. Volume diagnosis requires a large amount of diagnosis results to be produced within a reasonable time. However, it is challenging to achieve the desired throughput for modern designs with continuously increasing size. In this paper, we propose a method to partition a design under diagnosis into blocks together with a diagnosis flow at the block level. The diagnosis throughput is improved because more diagnosis jobs can be run concurrently and each job runs faster due to the reduced memory. A measure is also proposed to estimate the impact on diagnosis caused by design partitioning. Experimental results on benchmark circuits and several industrial designs show that diagnosis using circuit blocks has minimal impact on diagnosis accuracy and resolution. It is also demonstrated that the proposed measure is a good metric in predicting the impact on diagnosis.

In Automotive business, the quiescent supply current test (IDDQ) is a widely used and valuable test method to screen out production failures and reach the required low defective parts per million (DPPM) quality targets. Automatic Test Pattern Generation (ATPG) tools can generate scan based IDDQ patterns with high test coverage for Pseudo Stuck-At (PSA) faults. Functional pass but IDDQ failing devices need to be diagnosed for various purposes. In this paper a fast simulation based method is proposed to diagnose IDDQ failures with single or multiple defects for digital circuitry. The results are verified on real silicon for several 130nm Automotive designs. Furthermore automation of the diagnosis method for high volume diagnosis similar to scan volume diagnosis is shown in the paper outlook.

This paper introduces a novel Test Access Mechanism (TAM) for chips with multiple isolated identical cores through which all the cores can be tested in parallel and at the same time accurate failure diagnosis can be achieved while requiring similar test resources (tester memory and tester channels) as for a single core. The proposed pipelined architecture relies on forming nonlinear equations on a very limited number of output pins that compress the outputs from the identical cores and solve them off-chip to reproduce the failure information of each core. A very nice feature of the proposed scheme is that the number of observation pins required to achieve a desirable level of diagnostic resolution does not scale with the number of identical cores and can practically be kept constant.

The Standard Delay Format (SDF) information is very important in timing-aware simulation of VLSI designs. However, conventionally, SDF is only design-dependent, but pattern-independent, which is called static SDF in this paper. Static SDF ignores all dynamic pattern dependent parameters, such as IR drop and crosstalk. In this paper, we propose a novel pattern-dependent SDF (called dynamic SDF) generation technique, and apply it to take IR-drop effects into consideration. With the proposed IR-drop-aware SDF generation technique, we improve the accuracy of simulation, and perform diagnosis on the failed patterns to pin point the pattern-dependent IR-drop defects in our design. Experimental results demonstrate the efficiency of this method when used for transition delay fault pattern application and diagnosis.

For two-pattern at-speed scan testing, the excessive power supply noise at the launch cycle may cause the circuit under test to malfunction, leading to yield loss. This paper proposes a new weight assignment scheme for logic switching activity; it enhances the IR-drop assessment capability of the existing weighted switching activity (WSA) model. By including the power grid network structure information, the proposed weight assignment better reflects the regional IR-drop impact of each switching event. For ATPG, such comprehensive information is crucial in determining whether a switching event burdens the IR-drop effect. Simulation results show that, compared with previous weight assignment schemes, the estimated regional IR-drop profiles better correlate with those generated by commercial tools.

In prior work, profiling-based chain diagnosis methodologies were developed. This paper discusses the challenges associated with profiling-based chain diagnosis in the production test environment with limited failure buffer capacity on tester. We propose the following two pattern masking application flows to enhance diagnosis resolution in this scenario: (1) generic pattern masking and (2) adaptive pattern masking. Experimental results illustrate that pattern masking will enable profiling-based scan chain diagnosis in volume diagnosis environment.

In this work, we propose a method to improve diagnosis results when multiple physical defects are present in circuits under diagnosis. To improve diagnosis results when multiple defects are present in a circuit under diagnosis, the proposed method includes (i) analyzing relations among locations of logic faults and their diagnostic metrics to carefully derive physical faults, (ii) a new set covering procedure and (iii) a method to assign scores to faults to derive candidate sets of faults. Experimental results on several industrial designs and several cases of silicon defects show the effectiveness of the proposed diagnosis method.

Power supply noise may have big impacts on the design performance in the latest technologies. Accurately mapping the IR-drop effect to real delay is a challenging task, which will directly impact the accuracy of IR-drop related performance evaluation, test, and diagnosis. In this paper, we first present our previous work on setting up an IR2Delay database for addressing this issue. We then propose a flow to validate this database by comparing it with full-circuit SPICE simulation results. In this flow, mixed-signal simulation is used, which can reuse the existing digital testbench as stimuli while maintaining the accuracy of SPICE simulation.

Speedpath debug is a critical step in improving clock frequency of a design to meet the performance requirement. However, speedpath debug based on functional patterns can be very expensive. In this paper, we explore scan-based speedpath debug techniques based on at-speed scan test patterns. Several enhancements are implemented to improve over an earlier proposed scan-based speedpath diagnosis algorithm. We further report the application results by applying the improved algorithm to a leading-edge high performance microprocessor design.

Analysis of power grid IR-drop during scan test application has drawn growing attention because excessive IR-drop may cause a functionally correct device to fail at-speed testing. The analysis is challenging since the power grid IR-drop profile depends on not only the switching cells locations but also the power grid structure. This paper presents a scalable implementation methodology for quantifying the IR-drop effects of a set of switching cells. An example of its application to guide power-safe scan pattern generation is illustrated. The scalability and effectiveness of the proposed quantitative measure is evaluated with a 130 nm industrial design with 800 K cells.

In this poster, we share our industrial experiences on running chain diagnosis and PFA (Physical Failure Analysis) on a wafer that suffered from low yield. In addition, case study on PFA will be illustrated.

Extraordinary power consumption during the scan test may inadvertently cause a functional good die to fail. This paper proposes a peak power reduction algorithm for the scan test which considers both the shift cycles and capture cycles simultaneously to limit the peak power of all test cycles during the test generation. In addition, the analysis also recommends the types of circuit structures that are more suitable to add test logic for maximum power reduction with the minimum test cost. The proposed methodology is highly efficient and can be applied to large industrial designs.

Power dissipation in digital circuits during scan-based test is generally much higher than that during functional operation. Unfortunately, this increased test power can create hot spots that may damage the silicon, the bonding wires, and even the package. It can also cause intensive erosion of conductors-severely decreasing the reliability of a device. Finally, excessive test power may also result in extra yield loss. To address these issues, this paper first presents a detailed investigation of a benchmark circuit's switching activity during different modes of operation. Specifically, the average number of transitions in the combinational logic of a benchmark circuit during scan shift is found to be approximately 2.5 times more than the average number of transitions during the circuit's normal functional operation. A DFT-based approach for reducing circuit switching activity during scan shift is proposed. Instead of inserting additional logic at the gate level that may introduce additional delay on critical paths, the proposed method modifies the design at the register transfer level (RTL) and uses the synthesis tools to automatically deal with timing analysis and optimization. Our experiments show that significant power reduction can be achieved with very low overhead.

In the past, software based scan chain defect diagnosis can be roughly classified into two categories (1) model-based algorithms, and (2) data-driven algorithms. In this paper we first analyze the advantages and disadvantages of each category of the chain diagnosis algorithms. Next, an adaptive signal profiling algorithm that can use manufacturing ATPG scan patterns is proposed for scan chain diagnosis. Finally, several case studies and their PFA results are presented to validate the accuracy and effectiveness of the proposed algorithm.

In this paper, we present test generation procedures to improve scan chain failure diagnosis. The proposed test generation procedures improve diagnostic resolution by using multi-cycle scan test patterns. A diagnostic test generation flow to speed up diagnosis is proposed to address the issue of long run times of test generation and large number of test patterns for the cases where the range of suspected cells is large. Experimental results on several industrial designs show the effectiveness of the proposed procedures in improving diagnostic resolution, reducing run times of test generation and also reducing the number of test patterns.

An at-speed scan test methodology is proposed for the purpose of the timing optimization and calibration. The proposed method, called TOC-ATPG, addresses both undertesting and overtesting issues of the traditional at-speed scan-based structural test. A pseudo-random pattern-based circuit analysis is first applied to analyze the potential glitches and transitions due to the functional illegal states. A list of state elements to be constrained during ATPG to prevent the sensitization of the functional illegal transitions and glitches are derived. During ATPG the derived constraints are applied to prevent overtesting, and timing-aware transition fault approach is used simultaneously to detect the fault through the timing critical paths to overcome the undertesting issue. The proposed method demonstrates very high correlation to the purely sequential test in functional mode with bounded run time overhead and can be applied to very large design.

To reduce test data volumes, encoded tests and compacted test responses are widely used in industry. Use of test response compaction negatively impacts fault diagnosis since the errors in responses due to defects which are captured in scan cells are not directly observed. We propose a simple and effective way to enhance the diagnostic resolution achievable by production tests with minimal increase in pattern counts. In this work we present experimental results for the case of multiple scan chain faults to demonstrate the effectiveness of the proposed method.

Speed path debug is a critical step to improve the performance of high performance VLSI designs. The purpose of speed path debug is to identify the performance limiting paths and fix them in the next product stepping so that the chip can run at a higher clock frequency. This paper investigates speed path debug techniques using at-speed scan test patterns. For each failing scan cell, the failing paths are identified based on structural analysis of logic simulation values. We further propose two metrics to rank the identified speed paths based on logic value analysis and based on timing information calculated for the failing pattern. Experimental results show the effectiveness of the proposed speed path debug technique.

With nanometer processes, at-speed testing is required to filter out failing chips with delay defects to ensure high product quality. Locating delay defects is important not only for improving yield but also providing important information to enhance at-speed test methods to meet quality goals. In this paper, a method that leverages successful static defect diagnosis method to diagnose delay defects is presented. To avoid missing any defect suspects, transition fault model is used with special considerations of self masking, glitch detection and passing bit mismatch. The effectiveness of this approach is demonstrated with simulation experiments as well as two case studies on failing chips from Renesas Technology's 130nm process.

For volume production of VLSI designs in future technologies fast and accurate diagnosis of manufacturing defects on a large number of chips is necessary to ramp up yields. Methods to speed up commonly used effect-cause fault diagnosis procedures have been recently proposed. These include the use of fault response dictionary. However, for very large industrial designs, these methods either need very large dictionaries or they drastically reduce the speedup achievable by using dictionaries. In this work we propose a method to achieve higher speedup with small sized dictionaries. We achieve this by identifying a set of faults called hyperactive faults for which we create a novel dictionary. Experimental results are presented to demonstrate the effectiveness of the proposed method.

This paper describes a robust scan pattern mismatch debugger for the scan pattern validation process. Simulation mismatches observed during scan pattern validation process need to be resolved before scan pattern can be used in silicon. In this framework, we use efficient structural cone to create VCD values from a timing-based simulator. The VCD values are then used to trace the mismatches from failing observation points to the mismatch sources. Root-cause analysis is then performed by combining all mismatch source instances to conclude the most likely mismatch reasons. Comparing to existing solutions, the proposed mismatch debug flow doesnpsilat require VCD values of all signals in the designs, nor does it require multiple simulation of the test patterns in the Verilog simulator. Experimental results show the effectiveness and efficiency of the proposed scan pattern mismatch debug flow.

Prior effect-cause based chain diagnosis algorithms suffer from accuracy and performance problems when multiple stuck-at faults exist on the same scan chain. In this paper, we propose new chain diagnosis algorithms based on dominant fault pair to enhance diagnosis accuracy and efficiency. Several heuristic techniques are proposed, which include (1) double candidate range calculation, (2) dynamic learning and (3) two- dimensional space linear search. The experimental results illustrate the effectiveness and efficiency of the proposed chain diagnosis algorithms.

In this paper, we study the impact, detection and diagnosis of the defect inside a scan cell, which is called scan cell internal defect. We first use SPICE simulation to understand how a scan cell internal defect impacts the operation of a single scan cell. To study the detectability and diagnosability of a scan cell internal defect in a production test environment, we inject scan cell internal defects into a scan-based industrial design and perform fault simulation by using production scan test patterns. Next, we evaluate how effective an existing scan chain diagnosis technique based on traditional fault models can diagnose scan cell internal defect. We finally propose a new diagnosis algorithm to improve scan cell internal defect diagnostic resolution using scan cell internal fault model. Experimental results show the effectiveness of the proposed scan cell internal fault diagnosis technique.

We present a flow to extract, simulate and generate test patterns for interconnect open defects. In contrast to previous work, the accuracy of defect modeling is improved by taking the thresholds of logic gates as well as noise margins into account. Efficient fault simulation is enabled by employing an aggressive fault collapsing strategy and an optimized fault list ordering heuristic which allows to combine the advantages of event-driven simulation with bit parallelism. Test generation complexity is kept in check by generating patterns for technology-independent segment-stuck-at faults first, thus reducing (though not completely eliminating) the need for sophisticated technology-aware test generation. Moreover, a comprehensive untestability analysis identifies new classes of untestable faults. Experimental results demonstrate high efficiency of the new flow, outperforming earlier work by two orders of magnitude.

Yield enhancements in the manufacturing process today require an expensive, long and tedious physical failure analysis process to identify the root cause. In this paper we present Axiom, a new technique geared towards efficiently identifying a single dominant defect mechanism (for example in an excursion wafer) by analyzing fail data collected from the production test environment. Axiom utilizes statistical hypothesis testing in a novel way to analyze logic diagnosis data along with information on physical features in the design layout and reliably identify the dominant cause for yield loss. This new methodology was validated by applying it to a single excursion wafer produced on a 90 nm process, in which the dominant failing physical feature was correctly identified.

Power consumption during scan-based test becomes a concern in nanometer technologies. Previous test power reduction techniques that insert additional logic in gate-level circuits may result in timing violations. In this paper, we show that the problem can be solved at the RTL instead so that the timing and area constraints will be handled automatically by synthesis tools. Using a signal probabilistic approach proposed previously, we identify power-sensitive scan cells at the prototyping gate level, and we map these cells to their corresponding signal/variable bits at the RT-level. Additional RTL code is added to freeze these power- sensitive bits in order to reduce scan shift power consumption. Experimental results on ITC99 benchmarks show that on average more than 22% power reduction can be achieved when we only freeze the top 1% of power-sensitive bits at RTL. The flow is more practical in terms of timing closure than doing the same at the gate-level.

We present a fully automated flow to generate test patterns for interconnect open defects. Both inter-layer opens (open- via defects) and arbitrary intra-layer opens can be targeted. An aggressor-victim model used in industry is employed to describe the electrical behavior of the open defect. The flow is implemented using standard commercial tools for parameter extraction (PEX) and test generation (ATPG). A highly optimized branch-and bound algorithm to determine the values to be assigned to the aggressor lines is used to reduce both the ATPG efforts and the number of aborts. The resulting test sets are smaller and achieve a higher defect coverage than stuck-at n-detection test sets, and are robust against process variations.

This paper presents X-Press - a new two-stage test-response compactor that can be easily integrated with a multiple scan-chain environment. This compactor preserves all benefits of spatial compaction and offers, due to its overdrive sequential section, compression much higher than the ratio of scan chains to compactor outputs. X-Press is also capable of handling a wide range of unknown (X) state profiles by deploying a two-level scan-chain-selection mechanism. In addition to a new compactor architecture, original contributions of this paper include a detailed analysis of two-level error masking caused by X states and a new algorithm to both rank scan chains and then to determine, in per-pattern mode, scan-chain-selection rules used to suppress X states. Experimental results obtained for a variety of designs show feasibility and efficiency of the proposed compaction scheme, altogether with actual impact of X states on a test-pattern count. Finally, diagnostic capabilities of the proposed scheme accompanied by further experimental results are also analyzed.

In this paper, we present a fault dictionary based scan chain failure diagnosis technique. We first describe a technique to create small dictionaries for scan chain faults by storing differential signatures. Based on the differential signatures stored in a fault dictionary, we can quickly identify single stuck-at fault or timing fault in a faulty chain. We further develop a novel technique to diagnose some multiple stuck-at faults in a single scan chain. Comparing with fault simulation based diagnosis technique, the proposed fault dictionary based diagnosis technique is up to 130 times faster with same level of diagnosis accuracy and resolution.

In this paper, we propose a novel RTL testability analyzer based on logical virtual prototyping. A very fast synthesis engine is utilized to create a gate level hierarchical netlist with generic gates, which we call a logical virtual prototype, in this paper. Subsequently, ATPG and testability analysis are performed on the logical virtual prototype to provide RTL designers with a wealth of information that would allow them: (1) Accurately estimate / predict test coverage. (2) Generate patterns that can be used for gate-level design. (3) Identify hard-to-test design blocks in RTL, which can then be redesigned to improve coverage.

This paper presents a programmable approach for performing scan-based logic built-in self test. This approach combines the techniques of reseeding and weighted random patterns testing. Reseeding is used to encode the bias cube and weighted patterns are used to fine tune the weight set. Experimental results show fault coverage comparable to ATPG can be achieved. Most importantly, the scheme fits well in the system test environment and high fault coverage can be obtained with a small number of reconfigurations on the BIST controller.

Effect-cause diagnosis procedures are the most commonly used in industry to diagnose VLSI circuits that fail manufacturing test or field applications. Fast and effective diagnosis procedures are essential to diagnose large numbers of failing dies for yield ramp-up. We have recently proposed a method to speed up effect-cause diagnosis procedures by using a dictionary of small size [26]. In this paper we propose methods to further reduce the dictionary size and still achieve higher performance. Experiments on several industrial designs demonstrate that, on average, effect-cause diagnosis procedures can be speeded up by 3.5X while requiring minimal memory overhead for a very small dictionary.

As technologies move below 130nm, the IC industry has seen a significant change in defect type encountered. Feature-related defects are becoming more prevalent than particle-driven defects in nanometer designs. The process and design variances require checks for the design-for-manufacturing (DFM) issues in order to achieve a high yield. Scan diagnosis targeted for the nanometer designs can provide quick, accurate and reliable failure information from the production environment. The ranked, fault classified and physically linked scan diagnosis results can, in turn, provide the guides for DFM checks. High volume diagnosis provides data to yield management system for statistical analysis. This presentation briefly explains the technology behind the scene, discusses scan diagnosis applications and shows the results.

In this paper, we present a test generation algorithm to improve scan chain failure diagnosis resolution. The proposed test generation algorithm creates a complete test set that guarantees each defective scan cell has unique failing behavior. This algorithm handles stuck-at fault and timing fault models. Problems and solutions that may happen in practical usage are discussed. We further extend the test generation algorithm to handle multiple failing scan chains and designs with embedded scan compression logic. Experimental results show the effectiveness of the proposed diagnostic test generation algorithm.

Scan based diagnosis can be of great help to guide physical failure analysis, which is critical for the success of silicon debug and yield ramp up. In practice, diagnosis becomes more difficult if scan chain defects and system logic defects co-exist on one die, which are called compound defects in this paper. We first describe the challenges in diagnosing this type of compound defects. A novel diagnosis flow is proposed to diagnose the compound defects on scan chain and system logic. The diagnosis methodology was successfully applied in industrial designs.

We consider the problem of determining the location of open defects in interconnects of deep submicron (DSM) designs. The target defect sites for this work are the vias in interconnects which are known to be defect prone. It is known that in DSM designs below 90 nm technology the circuit parameters may vary widely from nominal or design values and process variations make them less predictable. Thus it becomes necessary to develop methods for locating defect sites without accurate knowledge of circuit parameters. Logic diagnosis which is based on gate level net lists is one such method but the resolution of defect sites obtained by logic diagnosis is considered to be unacceptably low for locating open vias. We investigate a procedure that uses minimal information beyond the net lists and give experimental results to demonstrate the defect resolution obtained using the method. The additional information used by the proposed method is a list of nodes in the neighborhoods of circuit nodes and the circuit layout. Specifically, difficult to determine circuit parameters of manufactured instances of a design such as coupling capacitances between circuit nodes and threshold voltages of gates in the circuit are not needed to use the proposed diagnosis procedure.

In this paper we present practical techniques that enable diagnosis of defective library cells in a failing die. Our technique can handle large industrial designs and practical situations like compressed test patterns with multiple exercising conditions per pattern and sequence dependent defects. Being able to accurately differentiate between cell-internal and interconnect defects leads to a faster root cause failure analysis at a reduced cost. This capability was applied on an AMD graphics chip using 90nm at TSMC. In all of the failing dies that underwent physical failure analysis, the defective library cell identified by diagnosis was verified to be correct by failure analysis. Currently this capability is successfully used to diagnose another design using TSMC’s 65nm technology.

In this paper we present a new technique to speed up the effect-cause defect diagnosis by using a dictionary of very small size. In the proposed method, a dictionary of small size is used to reduce the number of events (gate evaluations) during the simulation of failing patterns and also a procedure to select a subset of passing patterns for simulation. Although the dictionary size is smaller, experimental results show speed up of effect-cause diagnosis by up to 156times. Experimental results from industrial designs validate the effectiveness of the proposed method.

Field programmable memory BIST controllers are becoming a necessity to target manufacturing defects in embedded memories. For 65nm and below, random defects are not the only ones affecting the yield of a process. Systematic as well as parametric defects are now the predominant causes of memory failures and have to be addressed. Conventional memory BIST algorithms are usually targeted to catch random defects. In order to catch such systematic and parametric defects, it is necessary to have the flexibility to apply new algorithms to embedded memories after manufacturing. In this paper, a field programmable memory BIST architecture is proposed to support multiple loops within a test step of an algorithm, including nested loops. These controllers, therefore, guarantee supporting complex algorithm necessary to target defects during failure analysis that could help yield ramp up or reduce test escapes. In addition, the proposed architecture is modular in nature and allows optimizing the complexity of the controller along with area and performance

The need for faster and more reliable yield ramp-up when introducing new CMOS technologies is driving the effort to acquire and analyze valuable information from production test, for the process of identification of yield detractors. This paper addresses a key step in the phase of "industrialization" of these processes: standardization. The objective of standardization is to enable a seamless flow for production integrated scan diagnosis in a multi-tool, multi-vendor environment. To make analysis of chips failing the production test more efficient, a process flow and a file format to store the failing response of the chips is proposed. This enables a smooth exchange of production test data from ATE to diagnosis, failure analysis, design and process

Circuit behavior in the presence of interconnect open defects is affected by four major factors: the capacitances between the floating node and its neighboring nodes, the capacitances inside down-stream gates, initial trapped charge, and the threshold voltages of down-stream gates. Current interconnect open diagnosis methods either ignore all of these factors or consider a subset of them only. Thus the diagnosis results from current procedures may not be as accurate as possible. In this paper, we present an interconnect open defect diagnosis method taking all these factors into account. Experiments conducted on benchmark circuits demonstrate that the proposed method can achieve a very high diagnosis accuracy and resolution

This paper presents a new approach for performing logic BIST diagnosis exclusively using MISR signatures. Unlike conventional logic BIST diagnosis approaches which require either huge test time or complicated logic BIST design and ATE flow, signature based diagnosis does not require dynamically changing MISR operations for each failing device. Our experimental data shows that signature based diagnosis can achieve similar diagnosis resolution with manageable diagnosis run time while eliminating most of the complexity associated with the traditional approach to logic BIST diagnostics

This paper discusses the challenges associated with diagnosing chain integrity and system logic failures in the production test environment with limited failure information. The following three methods were proposed to enhance diagnosis resolution in this scenario: (1) static pattern re-ordering (2) dynamic pattern re-ordering (3) per-pin based diagnosis. Experimental results illustrate that per-pin based failure logging and diagnosis algorithms enable scan chain diagnosis in volume production environment. Successful application of per-pin based chain diagnosis is demonstrated with an industrial case

The paper presents a two-stage test response compactor with an overdrive section and scan chain selection logic. The proposed solution is capable of handling a wide range of X state profiles, offers compaction much higher than the ratio of scan chains to compactor outputs, and provides excellent diagnostic resolution

As electronic design feature sizes continue to shrink and clock speeds continue to rise, more and more companies have turned to at-speed test techniques to help ensure high test and product quality. Due to incomplete timing information during automatic test pattern generation (ATPG), it is possible that some at-speed patterns may activate paths which are not required to meet system speed, and these patterns may fail during production test. It is often difficult and time consuming to identify these paths manually. This paper describes how to use diagnosis techniques to automatically identify these paths. Using this approach, the authors found most of these paths were false or multicycle paths inside DFT logic. These could be fixed by enhancing the timing exception paths used during ATPG to mask out transition values through these paths. Elimination of these paths resulted in a 300 MHz increase in the speed of the transition fault test pattern. However, occasionally the authors did find some failing paths were real functional problems and design changes were needed to resolve them

Software-based scan chain fault diagnosis is typically composed of two steps. First, scan chain flush patterns are used to identify faulty chains and fault models. This is followed by chain diagnosis using scan patterns in the second step. In this paper, we target chain diagnosis on one special category of chain faults: intermittent scan chain faults. It is showed that these faults may not be modeled correctly in the first step. Hence, a novel diagnosis methodology based on scan chain fault model relaxation is proposed.

Reduced pin count testing (RPCT) has proven to be an effective solution to reduce structural test costs in a manufacturing environment. Traditionally, RPCT has focused on stuck-at faults and IO loop-back tests. However, as circuit feature sizes shrink and new technology nodes employed, at-speed tests are becoming critical to assure low defect levels. In this paper, we extend the RPCT technique to allow application of atspeed test patterns using low cost testers that are seriously pin limited. Existing boundary scan cells are modified to facilitate the application of at-speed patterns thereby having minimal impact on the design and test area overhead.

Circuit behavior in the presence of bridge defects is affected by three factors: bridge resistance, drive strength of bridged signals and the threshold voltages of downstream gates. Current bridge defect diagnosis methods either ignore all of these factors or consider drive strengths and/or threshold voltages only. Specifically, existing diagnosis methods have not considered the effect caused by bridge resistance. So the diagnosis results from current procedures may not be as accurate as possible. In this paper, we present a bridge defect diagnosis method taking all three factors into account. Experiments conducted on benchmark circuits and one industrial design demonstrate that the proposed method can achieve a very high diagnosis accuracy and resolution.

In this paper, a novel logic BIST (built-in self test) scheme with complementary weights is proposed. The BIST implementation combines random patterns with complementary-weight weighted patterns. A heuristic algorithm based on deterministic test set is developed to compute weight set with complementary weights. Hardware similar to bit-flipping is used to produce complementary weights. For random resistant ISCAS circuits, complete fault coverage can be achieved with very low hardware overhead. Experiments show that two complementary weights are sufficient for weighted random pattern testing and it presents a novel direction for exploiting weighted patterns.

A full-speed field-programmable memory BIST controller is proposed. The proposed instruction and architecture designs enable full-speed operation of not only March algorithms but also some non-linear algorithms that are becoming more and more important in modern memory testing, diagnosis, and failure analysis.

In scan based designs, 10%-30% defects are in scan chains. Hence scan chain fault diagnosis becomes an important process for silicon debug and yield ramp up. With embedded compression techniques getting popular, chain diagnosis on devices with the embedded compression techniques becomes a challenge. In this paper, we provide a general methodology that can be applied for performing chain diagnosis in the context of any embedded compression techniques with any existing chain diagnosis algorithms. The proposed methodology enables seamless reuse of the existing chain diagnosis infrastructure with compressed test data. Experimental results show that with compressed patterns, the chain diagnosis resolution can be enhanced up to one order of magnitude with only 25% of failure cycles collected from ATE, compared to the diagnosis results with uncompressed patterns.

Diagnosis of scan test fail data plays a crucial role in enhancing ramp up of new CMOS technology generations. To enable faster feedback it is preferable to establish a monitoring diagnosis methodology on the production test floor. This paper reports result of a study on using test time optimized compressed scan technology and associated new algorithms for fault diagnosis. Data is based on a system-on-a-chip (SoC) product that is manufactured using Infineon Technologies' 130 nm process. A comparison with uncompressed scan test and diagnosis shows feasibility of implementing a monitoring diagnosis flow with compressed scan test serving the high throughput test flow.

Using off-the-shelf error correcting codes for compacting test response (Patel, 2003) is attractive because it provides multiple error detection and diagnosis support in the presence of multiple unknowns. However, this technique is not easily incorporated in a conventional scan testing environment because handling unknowns requires special ATE support or test response postprocessing to determine if the test passed. In this paper we solve this problem using a novel technique, X-filter, which removes the effect of unknowns on compacted test response. X-filter achieves this by using only O(mx) additional hardware with mx inputs. (x=maximum number of unknowns that can be tolerated, m=number of bits in the compacted response). Unlike compaction methods that require creation of special codes (Mitra, 2004), (Wohl, 2003), X-filter is more flexible in terms of number of errors and unknowns handled, and it does not increase the number of output pins over those used by the error correcting code itself.

In scan test environment, designs with embedded compression techniques can achieve dramatic reduction in test data volume and test application time. However, performing fault diagnosis with the reduced test data becomes a challenge. In this paper, we provide a general methodology based on circuit transformation technique that can be applied for performing fault diagnosis in the context of any compression technique. The proposed methodology enables seamless reuse of the existing standard ATPG based diagnosis infrastructure with compressed test data. Experimental results indicate that the diagnostic resolution of devices with embedded compression is comparable with that of devices without embedded compression.

A new algorithm to diagnose intermittent scan chain fault in scan-based designs is proposed in this paper. An intermittent scan chain fault sometimes is triggered and sometimes is not triggered during scan chain shifting, which makes it very difficult to locate the fault sites. In this paper, we provide answers to three questions: (1) Why intermittent scan chain faults happen? (2) Why diagnosis of this type of faults is necessary? (3) How to diagnose this type of faults? The experimental results presented demonstrate that the proposed diagnosis algorithm is effective for large industrial designs with multiple intermittent scan chain faults.

This work presents a novel BIST (built-in self test) scheme with scan chain segmentation. In the scheme, a combination of pseudo random patterns and single-weight patterns have been applied to CUT (circuit under test). Scan chain is partitioned into multiple segments delimited by inverters. When a single weighted pattern is applied to a segmented scan chain, successive segments receive bit patterns with complementary weights. Several segment configurations may be required to achieve full fault coverage. In this scheme the control logic is inside the scan path and built-in self test can be implemented without compromising timing performance of CUT. Experiments show that our scheme can obtain very good fault coverage. Hardware implementation is simple and straightforward.

A memory BIST enhancement, ESP short for exercising system paths, is described that allows the efficiency and functional capabilities of standard approaches while addressing two important problems. Conventional Memory BIST techniques require MUXes at the inputs of the memory that allow for the inputs to be driven either by system signals or by test signals. These MUXes add delays, in the system path going to the memory, which often has critical timing. ESP eliminates such delays by implementing the MUXing function 'before' scan cells. ESP also uses scan cells to capture the memory output for feeding back to the BIST controller. This output may have traveled through some logic before getting to the recording scan cells. By including the delays of the system input and output paths, ESP allows for verifying that the memory will work correctly as part of the system rather than just as an isolated unit. Using ESP, a memory BIST can catch transition and delay faults that are impractical, or even impossible, to catch otherwise. Therefore, ESP can be useful for all memories but may be crucial for the memories which cannot tolerate the addition of the MUX delay to functional paths.

This paper presents a novel scan cell based control point insertion technique which eliminates timing degradation of conventional control points in built-in self test (BIST) applications. In this approach, control points are encoded into scan chains. Observation points are applied to enhance fault coverage. At each phase, a set of control points are activated to detect a set of target faults. Compared to conventional test point insertion, scan cell based control points improve controllability of the core logic without compromising timing performance of circuit under test (CUT). Experimental results show that close to stuck-at fault coverage by automatic test pattern generation (ATPG) can be achieved by our BIST method.

Critical paths are analyzed in a CAM and minimum test patterns are proposed to detect delay faults in a CAM. The test patterns derived are shown to be covered by the basic algorithm proposed earlier in (G. Giles et al, Proc. Int. Test Conf. p.471-474, 1985).

When VLSI design and process enter the stage of ultra deep submicron (UDSM), process variations, signal integrity (SI) and design integrity (DI) issues can no longer be ignored. These factors introduce some new problems in VLSI design, test and diagnosis, which increase lime-to-market, time-to-volume and cost for silicon debug. Intermittent scan chain hold-time fault is one of such problems we encountered in practice. The fault sites have to be located to speedup silicon debug and improve yield. Recent study of the problem proposed a statistical algorithm to diagnose the faulty scan chains if only one fault per chain. Based on the previous work, in this paper, an efficient diagnosis algorithm is proposed to diagnose faulty scan chains with multiple faults per chain. The presented experimental results on industrial designs show that the proposed algorithm achieves good diagnosis resolution in reasonable time.

This paper presents a method to embed an FPGA core in a SOC as an infrastructure IP that can exploit transaction-based verification methodology to verify and debug the first silicon. The primary objective for post-silicon verification is to reduce the time taken for validating the first silicon. Additionally, verifying silicon at chip-level is expected to speedup the silicon debugging and thus reduce the time to market. Experimental results presented in this paper demonstrate that the proposed method can be implemented with small overhead.

Intermittent scan chain hold-time fault is discussed in this paper and a method to diagnose the faulty site in a scan chain is proposed as well. Unlike the previous scan chain diagnosis methods that targeted permanent faults only, the proposed method targets both permanent faults and intermittent faults. Three ideas are presented in this paper. First an enhanced upper bound on the location of candidate faulty scan cells is obtained. Second a new method to determine a lower bound is proposed. Finally a statistical diagnosis algorithm is proposed to calculate the probabilities of the bounded set of candidate faulty scan cells. The proposed algorithm is shown to be efficient and effective for large industrial designs with multiple faulty scan chains. 1

Today’s ASIC designs consist of more memory in terms of both area and number of instances. The shrinking of geometries has an even greater effect upon memories due to their tight layouts. These two trends are putting much greater demands upon memory BIST requirements. At-speed testing and custom test algorithms are becoming essential for insuring overall product quality. At-speed testing on memories that now operate in the 10 to 800 MHz range can be a challenge. Another demand upon memory BIST is determining the location of defects so that the cause can be diagnosed, or repaired with redundant cells. A tool and methodology that meets these difficult requirements is discussed. 1

In this paper, a method is presented to schedule tests for core-based SoCs to achieve optimal test completion time for the SoC design by simultaneously determining optimal core clustering, core cluster wrapper width, and pin mapping. For the first time the above mentioned techniques are applied concurrently to solve the SoC test scheduling problem. A heuristic algorithm implementing these techniques to determine an optimal solution is proposed.

This paper presents a method to consider a given SOC with pin and peak power constraints, and simultaneously (1) determine an optimal wrapper width for each core, (2) allocate SOC pins to cores and (3) schedule core tests to minimize the test completion time. For the first time the stated problem is formulated as a restricted 3 dimensional bin-packing problem and a heuristic to determine an optimal solution is proposed.

A method to solve the resource allocation and test scheduling problems together in order to achieve concurrent test for core-based system-on-chip (SOC) designs is presented in this paper. The primary objective for concurrent SOC test is to reduce test application time. The methodology used in this paper is not limited to any specific test access mechanism (TAM). Additionally, it can also be applied for test budgeting during the design phase to obtain a tradeoff between test application time and SOC pins needed. In this paper, the above problem is formulated as a well-known 2-dimensional bin-packing problem. A best fit heuristic algorithm is employed to obtain satisfactory results.

This paper presents a methodology to insert scan paths in a functional Register Transfer Level (RTL) specification of a design that can exploit existing functional paths between sequential elements in the original circuit for establishing scan chains. The primary objective for RTL scan insertion is to reduce the time taken for DFT, and thus reduce the time to market. Additionally, building scan chains at the functional RT-Level is expected to reduce the total area overhead introduced by full scan without compromising the fault coverage achieved. In addition, it often eliminates the delay associated with the additional multiplexer as a part of a conventional scan-cell in high performance designs. Experimental results presented in this paper demonstrate that the proposed method achieves the above objectives while also achieving higher fault coverages for most of the benchmark circuits considered.

For current VLSI designs, there are two kinds of well-accepted digital testing technologies. One is for embedded memories and the other is for the logic. For embedded memories, Built-In-Self-Test (BIST) is used. For the logic, the main solutions are based on scan DFT and automatic test pattern generation (ATPG). However, to reduce the need to use an external tester, and to ease test reuse at the system level, more designs are using BIST to test logic. In the future, with system on chip (SoC) requirements and deep Sub-Micron (DSM) technologies, we believe that BIST and scan-based ATPG will continue to be the main solutions to VLSI testing. However, to be successful, some improvements are needed. The author discusses future trends in three categories: test quality, test application cost and test development effort.

We propose a new approach for implementing static compaction procedures for synchronous sequential circuits. The procedures we consider belong to the class of procedures that generate the compacted test sequence through restoration of segments (or subsequences) of a given test sequence T. Under the proposed approach, each restored segment detects a single target fault chosen from the faults detected by T at one time unit. A novel parallel pattern simulator is developed for this purpose. Experimental results for benchmark circuits are included.

High level ATPG does not make the test problem any easy. In fact, there are several design-flow-related complications it creates. Also, the fault models used in high level ATPG are not suitable. Gate level ATPG has dominated for over 20 years and continue to do so. And there are enough challenging unsolved problems in gate level ATPG and there is no evidence that high level ATPG provides any help to these challenging problems.

Scan test patterns are typically generated by ATPG tools which use a zero delay simulation model. These scan test patterns have to be verified using a golden simulator which is approved by the chip foundry with full timing before the patterns are accepted for manufacturing test. This can be very time consuming for many designs because of the size of the test data and the large number of test cycles which have to be simulated. A universal technique for accelerating scan test pattern simulation which can be used for any simulator with any scan cell type from any foundry is proposed. The extensions to test data languages to support universal acceleration of scan pattern simulation are also proposed. Some experiment results are also provided.

The problem of generating minimum test sets for diagnosing faults in wiring interconnects on printed circuit boards is addressed. It is assumed that all the nets can be accessed in parallel or through a boundary-scan chain on the board. The fault model includes multiple stuck-at-hand faults. Three methods for three different diagnosis mechanisms are presented. All the diagnostic methods can be further improved by taking advantage of the structural information of wiring interconnects.>

The authors describe PROOFS, a fast fault simulator for synchronous sequential circuits, PROOFS achieves high performance by combining all the advantages of differential fault simulation, single fault propagation, and parallel fault simulation, while minimizing their individual disadvantages. The fault simulator minimizes the memory requirements, reduces the number of gate evaluations, and simplifies the complexity of the software implementation. PROOFS requires an average of one fifth the memory required for concurrent fault simulation and runs six to 67 times faster on the ISCAS-89 sequential benchmark circuits.>

This paper describes PROOFS, a super fast fault simulator for synchronous sequential circuits. PROOFS achieves high performance by combining all the advantages of differential fault simulation, single fault propagation, and parallel fault simulation, while minimizing their individual disadvantages. PROOFS minimizes the memory requirements, reduces the number of events that need to be evaluated, and simplifies the complexity of the software implementation. PROOFS requires an average of one fifth the memory required for concurrent fault simulation and runs 6 to 67 times faster on the ISCAS sequential benchmarks.

The authors address the problem of generating minimum test sets for diagnosing faults in wiring interconnects on printed circuit boards. It is assumed that all the nets can be accessed in parallel or through a boundary-scan chain on the board. The fault model includes multiple stuck-at and short faults. Three methods for three different diagnosis mechanisms are presented. It is also pointed out that the self-diagnosis problem is the same as the concurrent error detection problem for asymmetric errors. Thus, the diagnostic methods considered are similar to the coding methods used in concurrent error detection. All the diagnostic methods can be extended to structural tests by taking advantage of the geometry of a circuit board to produce an efficient test.>

A new, fast fault simulator called differential fault simulator, DSIM, for sequential circuits is described. Unlike the concurrent fault simulation, DSIM simulates each machine by simulating its machine differences from the other machine just simulated instead of simulating its input differences from the previous status of the same machine. In this manner, DSIM simulates each machine (good or bad) separately for every test vector. Therefore, DSIM dramatically reduces the dynamic memory requirement and the overhead in the memory management in the concurrent fault simulation. Also unlike the single fault propagation which simulates each bad machine by simulating its machine difference from the good machine, the overhead to restore the good machine status before each bad machine simulation is eliminated in DSIM. Our experiments show that DSIM runs 3-12 times faster than an existing concurrent fault simulator and an experimental single fault propagation simulator. Furthermore, owing to the straightforward operations, DSIM is very easy to implement and maintain. Implementation consists of less than 300 lines of “C” language statements added to the event-driven true-value simulator in an existing sequential test generation system, STG. Currently DSIM uses a zero-delay timing model, while inclusion of other delay models is under development.

A test-generation algorithm called the BACK algorithm is proposed for sequential test generation. The BACK algorithm is a modified D-algorithm. Instead of forward fault propagation to generate sensitized paths, the BACK algorithm creates the sensitized paths backwards by justifying the required sensitized values. The BACK algorithm not only is easier to implement but also requires less run-time memory than the D-algorithm. A testability measurement which guides the justification of sensitized values is also presented. The BACK algorithm has been implemented and used very successfully for AT&T sequential circuits.>

Previous papers have shown that a ripple carry adder composed of several full adder cells can be completely tested by a minimum test set of size 8 independent of the number of cells in the ripple carry adder under single faulty cell assumption. The fault model assumed is that faults in a cell can change the cell behavior in any arbitrary way, as long as the cell remains a combinational circuit. In this paper, we assume that any number of cells can be faulty at any time. A minimum test set of size 11 which can detect arbitrary length ripple carry adders under this fault model is presented. For general (N, p) adders in which each cell is a p-bit adder, a minimum test set of size 3 × 22P − 1 is also presented.