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Wei-Chih Liu

dblp:23/4761 · DBLP profile ↗
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4ranked-venue papers
1as first author
0since 2021 · last 2012
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-authorDatabases, data management, data science and information retrieval · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test
0.222012
Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis · IEEE Trans. Computers 2012
Diagnosis of Multiple Scan Chain Timing Faults · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation › hardware verification and test › fault diagnosis
bridging fault diagnosis
0.112012
Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis · IEEE Trans. Computers 2012
Electronic design automation › hardware verification and test
fault diagnosis
0.112012
Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis · IEEE Trans. Computers 2012
Electronic design automation › hardware verification and test
fault simulation
0.112008
Diagnosis of Multiple Scan Chain Timing Faults · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation › hardware verification and test › fault diagnosis
test diagnosis
0.112008
Diagnosis of Multiple Scan Chain Timing Faults · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation › hardware verification and test › design for testability
scan-based testing
0.012012
Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis · IEEE Trans. Computers 2012

Methods — techniques the papers use, named apart from their topics

structural reduction · 0.1bridging pair extraction · 0.1parallel simulation · 0.1jump simulation · 0.1
YearPublicationVenuePosition
2012 Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis
abstract
This paper proposes four logic-chain bridging fault models, which involve one net in the combinational logic and the other net in the scan chain. Test results of logic-chain bridging faults, unlike existing scan chain fault models, depend on the previous scan inputs as well as primary inputs. A bridging pair extraction algorithm is proposed to quickly extract bridging pairs from the layout. The paper proposed two sets of structural reduction techniques so that runtime is very short. Experimental results on ISCAS benchmark circuits show that, on the average, logic-chain bridging faults can be diagnosed within an accuracy of four bridging pairs. The techniques are still applicable when there are only 10 failing patterns due to limited ATE failure memory. This paper demonstrates the feasibility to diagnose logic-chain bridging faults by software.
Wei-Lin Tsai, Wei-Chih Liu, Chien-Mo James Li
IEEE Trans. Computers2
2008 Diagnosis of Logic-to-chain Bridging Faults
abstract
We propose five logic-to-chain bridging fault models, which involve one net in the combinational logic and the other net in the scan chain. Test results of logic-to-chain bridging faults, unlike any existing fault, depend on the previous scan inputs as well as primary inputs. An accurate diagnosis technique is presented to locate logic-to-chain bridging faults. In addition, a bridging pair extraction algorithm is proposed to quickly extract bridging net pairs from the layout. Experimental results on ISCAS benchmark circuits show that, on the average, logic-to-chain bridging faults can be diagnosed within an accuracy of three bridging pairs. The technique is still applicable when only ten failing patterns are recorded on the tester.
Wei-Chih Liu, Wei-Lin Tsai, Hsiu-Ting Lin, Chien-Mo James Li
ITC1
2008 Diagnosis of Multiple Scan Chain Timing Faults
abstract
A diagnosis technique is presented to locate multiple timing faults in scan chains. Jump simulation is a novel parallel simulation technique which quickly searches for the upper and the lower bounds of every individual fault. The proposed technique takes into account the interaction of multiple faults so the diagnosis results are deterministic, not probabilistic. This technique is very useful in the production test environment because it requires only regular automated test pattern generator patterns, not specialized diagnosis patterns. Experiments on ISCAS'89 benchmark circuits show that this technique can successfully pinpoint almost every single one of 16 hold-time faults in a scan chain of more than 800 scan cells. The proposed technique is still effective when failure data are limited or faults are clustered.
Wei-Shun Chuang, Shiu-Ting Lin, Wei-Chih Liu, Chien-Mo James Li
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
2006 Visualizing the scientific world and its evolution
abstract
Abstract We propose an approach to visualizing the scientific world and its evolution by constructing minimum spanning trees (MSTs) and a two‐dimensional map of scientific journals using the database of the Science Citation Index (SCI) during 1994–2001. The structures of constructed MSTs are consistent with the sorting of SCI categories. The map of science is constructed based on our MST results. Such a map shows the relation among various knowledge clusters and their citation properties. The temporal evolution of the scientific world can also be delineated in the map. In particular, this map clearly shows a linear structure of the scientific world, which contains three major domains including physical sciences, life sciences, and medical sciences. The interaction of various knowledge fields can be clearly seen from this scientific world map. This approach can be applied to various levels of knowledge domains.
I. Samoylenko, T.-C. Chao, Wei-Chih Liu, Chi-Ming Chen
J. Assoc. Inf. Sci. Technol.3