With the advent of deep-submicrometer VLSI technology, the capacity and performance of semiconductor memory chips is increasing drastically. This advantage also makes it harder to maintain good yield. Diagnostics and redundancy repair methodologies thus are getting more and more important for memories, including embedded ones that are popular in system chips. In this paper, we propose an efficient memory diagnosis and repair scheme based on fail-pattern identification. The proposed diagnosis scheme can distinguish among row, column, and word faults, and subsequently apply the Huffman compression method for fault syndrome compression. This approach reduces the amount of data that need to be transmitted from the chip under test to the automatic test equipment (ATE) without losing fault information. It also simplifies the analysis that has to be performed on the ATE. The proposed redundancy repair scheme is assisted by fail-pattern identification approach and a flexible redundancy structure. The area overhead for our built-in self-repair (BISR) design is reasonable. Our repair scheme uses less redundancy than other redundancy schemes under the same repair rate requirement. Experimental results show that the area overhead of the BISR design is only 4.1% for an 8 K × 64 memory and is in inverse proportion to the memory size.

Next-decade computing power and interconnect bottle-neck challenge conventional IC design due to the ever increasing demands for high frequency and great bandwidth. Three-dimensional large-scale integration (3D-LSI) provides an opportunity to realize such high performance cores while reducing long latency. In this paper, we present a reference flow for the implementation of 3D via-last ICs in scalable face-to-back bonding style which leverages a mature set of 2D IC physical design tools. The first enabling technology of 3D-LSI is through-silicon via (TSV). Two kinds of TSV diameters are exemplified in the flow, namely, 5¿m and 50¿m. We propose an easy-to-adopt method to address the TSV-aware mixed-sized placement by considering the obstructions generated from adjacent-tier's floorplan, subject to certain TSV alignment constraints. Furthermore, the technique of clock tree synthesis (CTS) for a homogeneous die stack is developed to dramatically reduce the clock latency and skew. The mixed-sized placement and CTS of each tier can be done without iteration. To the best of our knowledge, no work has ever been published in literature discussing CTS for 3D via-last integration in a face-to-back fashion. Finally, to complete the proposed flow 2D timing-driven routing and modified off-line design rule check (DRC) and layout versus schematic (LVS) verification are performed very well.

In this paper, we propose a new test method to detect write disturbance fault (WDF) for magnetic RAM (MRAM). Furthermore, an adaptive diagnosis algorithm (ADA) is also introduced to identify and diagnose the WDF for MRAM. The proposed test method can evaluate process stability and uniformity. We also develop a built-in self-test (BIST) circuit that supports the proposed WDF diagnosis test method. A 1-Mb toggle MRAM prototype chip with the proposed BIST circuit has been designed and fabricated using a special${0.15}\hbox{-}\mu{\hbox {m}}$CMOS technology. The BIST circuit overhead is only about 0.05% with respect to the 1-Mb MRAM. The test time is reduced by about 30% as compared with the test method without using the decision write mechanism. The chip measurement results show the efficiency of our proposed method.

Random fluctuations in process conditions change the physical properties of parameters on a chip. The correlation of device parameters depends on spatial locations. In general, the closer devices most likely have the similar parameter variation. The key performance of many analog circuits is directly related to accurate capacitance ratios. Parallel unit capacitances have a great effect on reducing ratio mismatch. This paper addresses the impact of capacitance correlation on the yield enhancement of mixed-signal/analog integrated circuits. The relationship between correlation and variation of capacitance ratio is also presented. Therefore, both mismatch and variation of capacitance ratio can be expressed in terms of capacitance correlation. Furthermore, both process variation and device mismatch are considered in the early design phase to reduce the design costs and speed up the time to market.

To help improve quality and yield of magnetic random access memory (MRAM), we propose an adaptive diagnosis algorithm (ADA) that can efficiently identify the write disturbance fault (WDF) for MRAM. The proposed test algorithm is a Marchbased one, i.e., it has linear time complexity and can easily be implemented with built-in self-test (BIST). However, the proposed test method can evaluate the process stability and uniformity using logical test method. We also develop a BIST circuit that supports the proposed WDF diagnosis test method. We propose the BIST scheme based on the Decision Write mechanism of the toggle MRAM to reduce total test time. A 1Mb toggle MRAM prototype chip with the proposed BIST circuit has been designed and fabricated using a special 0.15µm CMOS technology. The BIST circuit overhead is only about 0.04% with respect to the 1Mb MRAM. The test time is reduced by about 30% as compared with the test method without using the Decision Write mechanism.

The random-like filling strategy pursuing high compression for today's popular test compression schemes introduces large test power. To achieve high compression in conjunction with reducing test power for multiple-scan-chain designs is even harder and very few works were dedicated to solve this problem. This paper proposes and demonstrates a multilayer data copy (MDC) scheme for test compression as well as test power reduction for multiple-scan-chain designs. The scheme utilizes a decoding buffer, which supports fast loading using previous loaded data, to achieve test data compression and test power reduction at the same time. The scheme can be applied automatic test pattern generation (ATPG)-independently or to be incorporated in an ATPG to generate highly compressible and power efficient test sets. Experiment results on benchmarks show that test sets generated by the scheme had large compression and power saving with only a small area design overhead.

The random-like filling strategy pursuing high compression for scan test introduces large test power. To pursue high compression in conjunction with reducing test power for multiple scan chain designs is even harder and very few works were dedicated to solve this problem. This paper proposes and demonstrates a multilayer data copy (MDC) scheme for test compression as well as test power reduction for multiple scan designs. The scheme utilizes a buffer, which supports fast load using previous loaded data, to achieve test data compression and test power reduction at the same time. The scheme can be applied ATPG-independently or to be incorporated in an ATPG to generate highly compressible and power efficient test sets. Experiment results on benchmarks show that test sets generated by the scheme had large compression and power saving with little area design overhead

The crosstalk fault becomes more and more important in the deep submicron SoC and its detection involves sophisticated timing measurement. In this paper, a new test scheme to detect the crosstalk fault, based on the path delay inertia, for interconnection lines in SoC is proposed. The scheme, without using timing measurement, applies a transition on the aggressor line and a critical width pulse, CWP, to the victim line and detects the propagation of the CWP at the output of the victim line. The scheme is simple and simulation analysis and experiments show that it is effective in detecting crosstalk faults.

With the advent of system-on-chip (SOC), the demand for embedded memory cores increases rapidly. The magnetic random access memory (MRAM) is considered one of the potential candidates that replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM has a high speed and does not need high supply voltage for read/write operations, so it has the advantages of RAM and flash memory, making it a potentially good choice for SOC. The testing of MRAM, however, has not been fully investigated. In this work we classify and analyze the MRAM defects and their behavior, and propose its fault models. We have built a SPICE model of MRAM cell and performed defect injection and simulation of a real MRAM circuit. The circuit has been implemented and fabricated with a novel 0.18 m technology. The simulation results regarding the correlation between the defects and conventional fault models show that most of the defects can be covered by the stuck-at fault model. The test data based on the fabricated chips show that the stuck-at faults do cover most of the defects on the chips. However, from the experiment we also have identified two new faults, i.e., the Multi-Victims fault and Kink fault.

This paper investigates detection and location for single faults in odd-even sorting networks. In the work, we have found that three tests are enough to locate single link fault and four tests are sufficient to detect single sorting element fault in an odd-even sorting network. For location tests for sorting element faults, the numbers of tests depend on the type of faults occurring at the sorting element. For most types of sorting element faults, the numbers are less than four specific tests. For the other types of faults, we have presented the test generation procedure and binary search procedures to generate the tests. The numbers of location tests are less than (n+log/sub 2/n), where n=log/sub 2/N and N is the number of inputs of the sorting network.

This paper presents a theoretical analysis to identify robust untestable path delay faults. It first classifies the path reconvergence of fanouts into seven cases and deduces the necessary conditions to robustly test path delay faults for each case. It then proposes a procedure, based on the deduced conditions, to identify the robust untestable path delay faults. The procedure was applied to ISCAS 85' circuits and it was found that the robust untestable faults occupy a high percentage of the total path delay faults. In addition, it also presents a method to estimate the number of robust untestable path delay faults for a circuit.

This paper firstly studies gate delay fault dominance relationships for the nortrobust and robust testings and presents fault collapsing procedures.A testability measure, based on a probability model, for the delay faults both for the nonrobust and the robust testings are proposed for combinational circuits and for sequential circuits.A program has been implemented based on the measure and applied to ISCAS benchmark circuits to estimate the fault coverages.The results are in good agreement with the experimental results obtained through fault simulation.I.