Motivated by the practical needs of simulation-based optimization, this paper considers a problem for selecting the best feasible design from a finite set of alternatives, subject to stochastic constraints given in several secondary objectives. We propose an efficient ranking and selection procedure that maximizes the accuracy of the selection under a limited simulation budget. The proposed procedure sequentially updates the simulation data of designs with a heuristic policy that allocates further simulation replications according to the evaluation results of data based on a statistical hypothesis test. Compared to recent studies, such as OCBA-CO and SCORE, this procedure can be more efficient when the simulation model involves large stochastic noise because its heuristic policy considers the precision of the sample mean ignored by the previous studies. Several experimental results of benchmarks demonstrate its improved efficiency, and a case study on the design of military network system shows its effectiveness for practical problems.

Stochastic simulation is beneficial when evaluating the performance of a complex system. When optimizing the system performance with the simulation, we need to make a final decision by considering various qualitative criteria neglected by the simulation as well as the simulation results. However, as simulations are expensive and time-consuming, in this paper, we propose a ranking and selection algorithm to make such optimization with the simulation efficient. The proposed algorithm selects a best-subset of designs expected to optimize the system performance from a finite set of alternatives. Furthermore, the algorithm identifies the ranking of designs within the subset. To maximize the accuracy of the selection under limited simulation resources, the algorithm selectively and gradually increases the precision of the sample mean of each design by allocating the resources heuristically based on the evaluated uncertainty. The selected subset allows decision makers to efficiently choose the best design that optimizes the performance while satisfying the qualitative criteria. We exhibit various experimental results, including a practical case study, to empirically demonstrate the efficiency and high noise robustness of the proposed algorithm.

This paper addresses the problem of selecting a Pareto set from among finite alternatives, where each alternative has multiple performance measures evaluated by stochastic simulations. Under limited simulation resources, we propose an efficient algorithm for solving this problem based on a statistical hypothesis test. Using the test, the proposed algorithm evaluates the uncertainty of each design based on the observed simulation results to identify whether the selected Pareto set is accurate. Based on the evaluated uncertainty, the algorithm assigns additional resources to the designs to maximize the accuracy of the selected Pareto set. Applying the sequential procedure, the algorithm increases the precision of the observed information selectively and gradually. Several experiments, including a practical case study, demonstrated its improved efficiency compared to the existing algorithms in the literature. This improved efficiency, along with low complexity and high robustness to noise, allows the proposed algorithm to be effectively applied to practical system designs.

During the development or deployment of discrete event simulation systems, many sudden changes in requirements emerge. To embrace the changes rapidly and reduce development costs, attaching reusable, and black-boxed components to existing systems has been regarded as one of the most effective approaches because modifications at the code level are generally costly and risky. However, since this approach requires components that are an exact fit, it may not be easy to avoid the modifications at the source code level actually. Moreover, the required components may not exist. Hence, this paper applies black-box extensibility to simulation systems in order to avoid the modifications. This paper proposes adaptive discrete event simulation systems using event control models for extending and modifying semantics through event-based simulation interface. With the proposed work, the simulation events are modulated, deleted, and generated by the event-oriented control functions in the event control model to embrace the changes of requirements. It can substitute for the modifications at the code level and extend the existing behavioral semantics. As a result, the proposed work provides a new alternative step in the development process with reusable components to avoid modifications at the source code level. The new step will lead to rapid adaptations of existing simulation systems. To support the effectiveness of this approach, this paper will describe applicable examples based on our empirical studies.

This paper proposes an improved algorithm for the optimal subset selection of a stochastic simulation model. The algorithm uses a statistical hypothesis test based on frequentist inference to evaluate the uncertainty about the selection, and it distributes simulation resources to designs for minimizing the uncertainty in each iteration. Several experiments demonstrate the improved performance compared to the other algorithms, and the performance increases significantly as the noise of the model increases. As a result, its high robustness to noise allows the algorithm to efficiently analyze real-world problems.

This paper proposes an efficient ranking and selection algorithm for a stochastic simulation model. The proposed algorithm evaluates an uncertainty to assess whether the observed best design is truly optimal, based on hypothesis test. Then, it conservatively allocates additional simulation resources to reduce uncertainty with an intuitive allocation rule in each iteration of a sequential procedure. This conservative allocation provides a high robustness to noise for the algorithm. The results of several experiments demonstrated its improved performance compared to the other algorithms in the literature. The algorithm can be an efficient way to solve optimization problems in real-world systems where significant noise exists.

In mixed-signal system-on-chip (SoC) design, distributed cosimulation is one of the practical approaches for unifying various abstracted hardware models using different description languages. Conventional ad hoc distributed cosimulation solutions do not have formal theoretical backgrounds of simulator integration into their solutions. In this brief, we propose a general cosimulation framework based on the high-level architecture (HLA) and newly defined programming language interface for interoperation (PLI-I) as a formal simulator interface. Based on the PLI-I and HLA, we propose formal integration and interoperation procedures. To reduce integration costs, the procedures have been developed into a common library and then merged with model-dependent signal-event converter to handle differently abstracted in/out signals. During the interoperation, to resolve the different time-advance mechanisms of the digital and analog simulators, the adapter executes an advanced HLA-based synchronization based on the presimulation concepts. The case study shows the reduced design effort in integrating and validating the heterogeneous models and simulators using the proposed framework in mixed-signal SoC design.

Simulation-based experiment of complex systems is a time consuming-job. Parallel and distributed simulation is one of the methods to reduce the simulation time. To simulate and analyze the system with this method, it is required to design a suitable experimental frame. Therefore, this paper proposes a MapReduce based experimental frame for the parallel and distributed simulation. Because Hadoop MapReduce is the most widely used parallel and distributed computing platform, we use it to design the experimental frame. In our work, the ‘map’ of MapReduce automatically generates and simulates the system, and the ‘reduce’ of MapReduce collects and analyzes the result. We can reuse the existing large scale Hadoop clusters without any modification of the platform, so it is easy to set-up and use the experimental frame. This paper presents an air defense simulation to show the usage and speed up with a 16-node Hadoop cluster.

M&S-based analysis has been performed for simulation experiments of all possible input combinations as a 'what-if' analysis causing the simulation to be extremely time-consuming. To resolve this problem, this paper proposes a multi-fidelity M&S methodology for enhancing simulation speed while minimizing accuracy loss and maximizing model reusability, in the M&S-based analysis. Target systems of this methodology are continuous and discrete event system. The proposed multi-fidelity M&S methodology consists of 4 steps: 1) target model selection and Interest Region definition, 2) low-fidelity model development, 3) multi-fidelity model composition, 4) selected target model substitution. Also this methodology proposes structure of multi-fidelity model and its mathematical specifications for the third step. This methodology is applied without any modification of existing models and simulation engine for maximizing model reusability. Case study applies this methodology to Torpedo Tactics Simulation model and the Vehicle Allocation Simulation model. The result shows that simulation speed increases at least 1.21 times with 5% accuracy loss. We expect that this methodology will be applicable in various M&S-based analysis for enhancing simulation speed.

Designing a mixed-signal integrated hardware requires the mixed simulation for legacy digital blocks and analog circuits, which are usually represented by the Verilog description language for digital blocks and the SPICE circuit netlist of analog circuits. Without model translations or source-level modifications and to simulate mixed legacy Verilog models and SPICE circuit netlists that are usually developed based on the different SPICE languages, parameters and primitives, this paper proposes a simulation framework whose concept is connecting a legacy Verilog and proper SPICE simulator for the target SPICE model using a run-time infrastructure (RTI) based on high level architecture (HLA) and adapters that are pluggable libraries to enable the interoperation and integration of simulators through HLA. For the interoperation, to exchange analog/digital signals, the adapter converts analog/digital signals to events or events to analog/digital signals using user-defined, signal-event converters. To synchronize different time advance policies, the adapter performs time synchronization procedures based on the pre-simulation concept. For the integration of Verilog/SPICE simulators and the RTI, adapters are developed following each component interface, which are IEEE-std Verilog procedural interface, proposed SPICE procedural interface and IEEE-std HLA interface. The proposed framework was applied to the digitally controlled buck converter simulation.

The bit-line sense amplifier (S/A) for on-chip flash memory compares cell current with reference current to identify data that are programmed. The S/A for 0 (erased) cell data consumes a large sink current, which is greater than off-current for 1 (programmed) cell data. This brief proposes a built-in write/read path based on binary inversion methods to reduce the sensing current of S/A. An original binary code is programmed into flash memory with an inverted binary code based on the proposed bit inversion techniques. The de-inversion hardware, which is implemented with small logic gates to restore original binary data, only consumes logic current instead of analog sink current in the S/A. The proposed techniques are evaluated for the DSPStone benchmark and are applied to the modified S/A for ARM Cortex-M3-based microcontroller with 128-kB on-chip flash memory based on a 0.18-um EEPROM technology. The circuit-level simulation result for the DSPStone benchmark shows that a newly implemented chip with the S/A based on the proposed technique consumes approximately less than 22% of the operating power that conventional S/A uses.

The 3-D TV active shutter glasses (SGs) technology requires the communication of the sync timing for time-sequential frame synchronization, in contrast to the syncless film-type patterned retarder approach. To advance our previous work based on the fractional-order timer, this paper proposes a fractional-order synchronizer, including an adaptive sync reconstructor (ASR) based on FRT for syncless frame synchronization. The FRT enables accurate synchronization regardless of sync-clock speed. The hybrid cooperation of FRT and ASR reduces the required frequency of communication of the sync packets and turns off the emitter on the TV side for perfect syncless operation. The implemented one-chip solution uses less than roughly 11% of the operating current of major commercial SG. The syncless SG technique also minimizes synchronization failure and 3-D vision crosstalk from interruption in sync packets.

The discrete event systems specification (DEVS) formalism supports the object-oriented (OO) specification of discrete event models in a hierarchical, modular manner. If a system that is to be modeled is domain-specific, the development of models with the use of the DEVS formalism would require domain knowledge about the system as well as to understand DEVS semantics. This paper proposes a collaborative modeling process to compensate for the lack of professional engineers. To compensate, this modeling process utilizes three types of engineers: domain engineer, modeling and simulation (M&S) engineer, and platform engineer. The process consists of four steps: conceptual modeling, model partition, model implementation, and model integration/simulation. The system requirements are used to specify domain models in the conceptual modeling step, and the models are partitioned into two types: discrete event-level model (DEM) and behavioral-level model (BM). The DEM is specified as the DEVS formalism, and the BM is defined as algorithms and equations. Each model is implemented separately, and the implemented models are integrated and simulated flexibly by using a dynamic linking library. The modeling process is then applied to develop a war game simulator. The advantage of this modeling process is that the collaborative work is related to the whole series of steps. This collaboration maximally utilizes the capabilities of the professional engineers by seamlessly separating yet correlating their works.

This paper presents a hierarchical federation system interconnected among federations and proposes a hierarchical federation composition algorithm that composes federations into different compositions of hierarchical federations and then efficiently assigns composite federations to a distributed environment while enabling information hiding. We implement the hierarchical federation system and evaluate it using real networks. The experimental results show that our composition algorithm performs better than a random composition algorithm in optimizing the composition of federations while achieving information hiding.

Multimedia and DSP applications have several computationally intensive kernels which are often off loaded and accelerated by application-specific hardware. This paper presents a speculative loop pipelining technique to overcome limitations of binary translation for hardware acceleration. Although many compilers have been developed at source level, it is desirable to translate the binary targeted to popular processors onto hardware for several practical benefits. However, the translated code can be less optimized. In particular, it is difficult to optimize memory accesses on binary to exploit pipeline parallelism since memory optimization techniques require perfect dependence information for correctness and efficiency. This information is not often available at binary level or even at the source level. Our technique synthesizes the pipeline with memory dependence speculation and postpones some phases of compilation by generating a small dependence analysis code or logic which makes use of runtime values. Such speculative optimization achieves the large amount of parallelism and does not depend on any user annotation. The experimental results show a promising speedup of up to 2.53 compared with the code in which memory accesses are not optimized in the pipeline fashion due to conservative memory analysis. In addition, we have evaluated our technique at hardware level implementation on FPGA devices and achieved comparable clock frequency and power consumption compared to a conservative method while achieving significant improvement in throughput.

In most reconfigurable architectures, reconfiguration overhead is a great bottleneck for repetitive reconfigurations. In this paper, we introduce a resource sharing algorithm exploiting static partial reconfiguration to reduce reconfiguration overhead between consecutive configurations. The proposed algorithm allows parameterizing reconfiguration overhead for individual resources. We also present both conservative and aggressive pruning techniques to reduce computation time. Experiments have been conducted with generated graphs and real benchmarks using a synthesizable intermediate representation. The results report that the algorithm could share up to 6.82% more resources than a previous interconnection sharing technique, and that the algorithm could reuse 80.9% resources in the selected benchmarks.

This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is a time-consuming task due to large design space, fast evaluation methodology for an architecture is crucial. We introduce the performance simulation model which can evaluate the performance without considering the functional correctness. This model has an FSM-like form and can afford to take all hazard types of pipelined architectures into consideration. The proposed approach is based on the property that an application program, especially multimedia application, has many iterative loops in general. This property invokes many iterative operations in the simulation. Evaluation reuse scheme can alleviate redundantly iterative operations of conventional simulators in the loop. A performance simulator for the pipeline architecture has been developed through which greater speedup has been made compared with other approaches in the evaluation of cycle counts.

This paper proposes a rapid evaluation scheme of pipeline architecture using phase-accurate simulation with only delay model and trace. With latency information for every stage, we can decide if an instruction in one stage can proceed to the next stage or if an instruction can be issued for each cycle without evaluating the value for registers. Branch target becomes available with trace generated by fast instruction set simulation. Fast verification time becomes possible because instruction set simulation is performed only once.

Real time simulation has time constraints within which certain model execution has to be completed. Such simulation usually has interactions with a surrounding environment, such as software components, hardware components or human operators. A proper scheduling policy for model execution and an associated method for feasibility analysis of real time execution are needed. This paper proposes a scheduling policy and its feasibility analysis method for real time discrete event system specification (RT-DEVS) models. The proposed analysis method consists of two phases: synchronization analysis and feasibility analysis. The former checks if the model specifications are consistent with their interactions. The latter examines feasibility for real time simulation of a given model under the proposed scheduling policy and a given hardware resource.

Model verification is to check the correctness of an implemented simulation program against a model specification. The paper proposed an automatic model verification methodology based on the I/O function level system morphism. The verification methodology establishes a mapping between all possible I/O event sequences of specification and those of implementation. The DEVS formalism is used as a specification language; implementation is assumed to be done by any simulation language or general purpose languages. Realization of the proposed methodology is presented with an example of verification for an assembly process model.

An ATM clustering system is a kind of workstation clusters over an ATM network. Such a system can be used as a distributed database server which requires reliable data delivery. This paper proposes an error recovery scheme at the transport layer for reliable data transfers with high throughput in the ATM clustering system. For such data transfers, acknowledgments are sent periodically as well as at the detection of packet losses. To be efficient the periods of acknowledgments for the scheme are adaptively varied depending on,whether current transfer is either in error-free phase or in an error recovery phase. The design and performance evaluation of the error recovery scheme is presented with a set of parameter values to achieve the best performance. The results show that the proposed scheme operates correctly and efficiently for the ATM clustering system. The throughput performance of the proposed scheme is superior to the SSCOP (service specific connection oriented protocol) regardless of packet loss rates.

Petri nets are a powerful modeling tool for studying reactive, concurrent systems. Analysis of the nets can reveal important information concerning the behavior of a modeled system. While various means for the analysis of the nets has been developed, a major limitation in the analysis, is explosion of large states space in simulation. An efficient method to manage large states space would overcome such a limitation. This paper proposes a framework for the modeling and analysis of Petri nets using relational database technologies. Formalism of the framework is based on a bag-theoretic relational algebra extended from the conventional, Within the framework, Petri nets are formalized by bag relations, and analysis algorithms are developed based on such formal relations. Properties associated with the nets are formalized by queries described in terms of the bag-theoretic relational algebra. The framework has been realized in a commercial relational database system using a standard SQL.

System entity structure (SES) is a structural knowledge representation scheme that contains knowledge of decomposition, taxonomy, and coupling of a system. Formally, the SES is a labeled tree with attached variable types that satisfy certain axioms. Described is a realization of the SES in Scheme (a Lisp dialect), that is called ESP-Scheme. Specifically, the computer representation of SES and main operations on SES are presented, and then facilities provided by ESP-Scheme are described. Two examples of application are discussed: a parallel processor model and a simulation study of a university phone registration system. ESP-Scheme acts as a model base management system in DEVS-Scheme, a knowledge-based simulation environment. It supports specification of the structure of a family of models, pruning the structure to a reduced version, and transforming the latter to a simulation model by synthesizing component models in the model base.>

This paper describes design and implementation of the hierarchical scheduling subsystem and graphical user interface in an intelligent environmental control system. The hierarchical scheduling system is capble of managing all environmental events occuring in widely different time scales as specified by the user. We employ a knowledge representation scheme called system entity structure to specify the environmental schedules in a hierarchical fashion. A system entity structure called TAL (Timed Action Language) is developed. TAL organizes a family of all possible long-/mid-/short-term schedules from which a specific schedule can be pruned by the user through graphical interface.