This paper describes a novel method that can be used to reduce test cycle count in a parallel access scan based built-in-self-test (BIST) environment. An algorithm that allows the efficient application of deterministically generated patterns is proposed. This approach allows BIST fault coverage to be increased using deterministic vectors, while minimizing the cost, in terms of test cycles, of applying the vectors.

In this paper, a complete functional testing of embedded ADC is presented. The integral non-linearity error, INLE, differential non-linearity error, DNLE, offset error, OSE, gain error and the signal-to-noise ratio, SNR are rested. The problem related to the propagation of the analog signal to the input of the ADC and the observation of the digital output of the converter at the output of the digital circuit are discussed. The two means for functional testing are discussed: the histogram and the FFT. To observe the outputs of the ADC at the digital circuit, the inverse function of the digital circuit is computed. This can be done by inverting the transfer function of the digital circuit whenever it is available. In the other case, when the digital circuit structure is available, the inverse of the digital circuit is found by boolean function manipulation.

Pseudoexhaustive BIST of sequential circuits consists of breaking all cycles in the circuit, partitioning the obtained acyclic circuit by placing some segmentation cells in the circuit, and balancing the partitioned circuit by introducing (or selecting in the scan path) additional flip-flops as delays in order to apply combinational TPG methods, In this paper, we present a new efficient method for pseudoexhaustive BIST. We first determine the flip-flops that cause the unbalanced structure of the acyclic circuit by using the peripheral retiming and, second, we use these flip-flops for the circuit partitioning. Thus, these flip-flops can be used for both partitioning and balancing problem of the circuit at the same time. We propose an algorithm for a partitioning problem which combines our idea with existing approaches.

In this work, we present a new approach for the pseudo-exhaustive BIST of synchronous sequential circuits. We first give a characterization of the flip-flops that cause the unbalanced structure of the acyclic circuit using peripheral retiming techniques, and, consequently, both logic optimization and balancing problem are considered and solved in the same phase. Second, the balancing solution is considered as a first step of the partitioning problem. For the remaining balanced circuit, the segmentation edges are selected such that there is a retiming minimizing the number of segmentation cells in the retimed circuit. Experimental results show that our approach significantly reduces the hardware overhead relative to the existing approaches.

In pseudo-exhaustive testing, the partitioning technique consists of placing segmentation cells in an acyclic sequential circuit in order to reduce the size of cones. These segmentations, which are transparent in normal mode and active during test mode, result in an overhead for the circuit. However, cutting edges containing registers eliminates these secondary effects. In this paper, we present a new approach to the partitioning problem of the synchronous sequential circuits based on the retiming technique. This approach consists in choosing a set of segmentation edges such that there exists a retiming minimizing the number of segmentation cells in the retimed circuit. Thus, for a given size limit of cone, we propose an iterative algorithm for pseudo-exhaustive sequential testing which combines our method with existing approaches. In addition, we prove that the proposed retiming can be considered as a peripheral retiming while at the same time integrating the logic optimization part in the partitioning process. Experimental results on the benchmark sequential circuits show that our approach significantly optimizes the retimed circuit and reduces the number of segmentation cells required in the original circuit.

A new approach for dynamic test vector compaction, for combinational logic circuits, called COMPACT, is proposed. A new data structure of test vectors permits easy verification of compactability between test vectors with minimal memory requirements. Experimental results obtained by adding the proposed algorithm to a simple PODEM program and applying it to the ISCAS-85 benchmark circuits are presented. The resulting test vector reduction is up to 40% for small circuits and around 50% for the large circuits (over 1000 gates).>