The sense margin available for sensing by the sense amplifier during the read access of 1T-1C FRAM cells affects the accuracy of the reading process. In this paper, a procedure for determining the sensing window of the 1T-1C FRAM cell will be discussed. Also, three proposed techniques for increasing the sense margin will be discussed.

Hardware Implementation of Data compression algorithms is receiving increasing attention due to exponentially expanding network traffic and digital data storage usage. Among lossless data compression algorithms for hardware implementation, Lempel -Ziv algorithm is one of the most widely used. The main objective of this paper is to enhance the efficiency of systolic- array approach for implementation of Lempel- Ziv algorithm. The proposed implementation is area and speed efficient. The compression rate is increased by more than 40% and the design area is decreased by more than 30%. The effect of the selected buffer's size on the compression ratio is analyzed. An FPGA implementation of the proposed design is carried out. It verifies that data can be compressed and decompressed on-the-fly.

This paper addresses the design of an analog very large-scale integration (VLSI) high accuracy neural cell with supervised learning ability using standard 2-/spl mu/m CMOS technology. A novel architecture is presented such that all cells, input, output, or hidden, have the same architecture which ensures a high degree of flexibility in terms of topology programming. Moreover, in designing the cell architecture, a new design technique based on hardware functionality multiplexing is employed. This technique resulted in a considerable compact cell. On the circuit level, the cell design is based mainly on a novel very high accuracy switched-current (SI) memory cell. With minor modifications, the SI memory cell is used in building all of the switched-current-based modules in the cell, which resulted in a high accuracy neural cell. The performance and timing for the separate modules and the whole cell are extensively studied. The cell is tested through a multi-layer perceptron network (MLP) using SPICE simulations to solve the digits-recognition problem.

The authors address the functional testing of microprocessors. A method is introduced for obtaining a minimum set of instructions that replaces the whole instruction set during testing procedure. The method is illustrated on the digital signal processor TM32010.>

In this paper, various fault location techniques in analog networks are described and compared. The emphasis is on the more recent developments in the subject. Four main approaches for fault location are addressed, examined, and illustrated using simple network examples. In particular, we consider the fault dictionary approach, the parameter identification approach, the fault verification approach, and the approximation approach. Theory and algorithms that are associated with these approaches are reviewed and problems of their practical application are identified. Associated with the fault dictionary approach we consider fault dictionary construction techniques, methods of optimum measurement selection, different fault isolation criteria, and efficient fault simulation techniques. Parameter identification techniques that either utilize linear or nonlinear systems of equations to identify all network elements are examined very thoroughly. Under fault verification techniques we discuss node-fault diagnosis, branch-fault diagnosis, subnetwork testability conditions as well as combinatorial techniques, the failure bound technique, and the network decomposition technique. For the approximation approach we consider probabilistic methods and optimization-based methods. The artificial intelligence technique and the different measures of testability are also considered. The main features of the techniques considered are summarized in a comparative table. An extensive, but not exhaustive, bibliography is provided.