This paper describes a novel and important use of a commercial Automatic Test Pattern Generation (ATPG) tool to perform formal verification during the design of the UltraSPARC/sup (TM)/-I and UltraSPARC/sup (TM/)-II microprocessors. The verification problem addressed in this paper is that of required signal constraints amongst a group of signals to ensure correct multiplexor operation. We do not address the equivalence between two representations of a design which is the more common problem in literature. The technique developed was a significant contributor to the overall success of the project. The problem addressed, solution formulation, software developed, and results are presented.

This paper describes the testability, debuggability, and manufacturability features of the UltraSPARC-I microprocessor. Due to the aggressive nature of this high performance design, these three areas needed to be addressed at the beginning of the project to ensure success. We present the goals and analysis that lead to our decisions as well as the actual features that were implemented. The features described in this paper have helped enormously in achieving the time-to-volume goals and hence the overall success of the product.

No abstract available.

With the anticipated growth of BiCMOS technology for high-performance ASIC design, the issue of testing takes on great significance. This paper addresses the testing of BiCMOS logic circuits. Since many different implementations of BiCMOS gates have been proposed, four representative ones are studied. The adequacy of stuck-at, quiescent current, and delay testing are examined based on circuit level faults. It is demonstrated that a large portion of the defects cannot be detected by common stuck-at or quiescent current tests since they manifest themselves as delay faults. By using the results presented, the test methodologies and the logic families can be ranked based on fault coverage. This ranking can then be used to help decide which BiCMOS solution is proper for a given application.>

The adequacy of the stuck-at fault model for BiCMOS logic is investigated. Realistic failures in basic logic blocks are examined, and their coverage by the stuck-at model is explored. It is shown that the static stuck-at model cannot cover the complete range of possible failures, and more importantly, tests for stuck-at faults will not detect realistic features in BiCMOS technology. This is because most open faults manifest themselves as delay failures. Through the use of transient analysis it is shown that the only way to insure proper functioning of BiCMOS circuits is to test for delay faults.>

The authors present a model that allows the designer to calculate the cost of scan-path design for testability (DFT) for standard cell-based chips. The model is used to estimate the profitability of designs that use DFT techniques over the product life cycle and those that do not. It is shown that, under dynamic market conditions, it is sometimes better to choose a more expensive solution if the product can be delivered faster. Thus, scan-path techniques can more than make up for their extra area if they reduce test generation time and therefore product lead times.>