Demo Data from VLDB 2026 / reviewers in the wild / expert
Seunghyun Lee 0003
dblp:23/774-3
· DBLP profile ↗
1ranked-venue papers
1as first author
1since 2021 · last 2025
0009-0000-5879-6599ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 33% Processor architecture and microarchitecture · 33% Electronic design automation · 33% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture › computer arithmetic
bit-serial arithmetic |
0.9 | 1 | 2025 | BitL: A Hybrid Bit-Serial and Parallel Deep Learning Accelerator for Critical Path Reduction · MICRO 2025 |
Electronic design automation › physical design › timing optimization
critical path reduction |
0.9 | 1 | 2025 | BitL: A Hybrid Bit-Serial and Parallel Deep Learning Accelerator for Critical Path Reduction · MICRO 2025 |
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.9 | 1 | 2025 | BitL: A Hybrid Bit-Serial and Parallel Deep Learning Accelerator for Critical Path Reduction · MICRO 2025 |
Methods — techniques the papers use, named apart from their topics
dynamic lookup switching · 0.9bit-wise multiply-accumulate · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | BitL: A Hybrid Bit-Serial and Parallel Deep Learning Accelerator for Critical Path ReductionabstractAs deep neural networks (DNNs) advance, their computational demands have grown immensely.In this context, previous research introduced bit-wise computation to enhance silicon efficiency, along with skipping unnecessary zero-bit calculations.However, we observe that existing bit-wise approaches miss an opportunity to optimize the critical computation path, as they process groups of values sequentially from the most significant bits (MSBs) to the least significant bits (LSBs).To address this limitation, we propose BitL, a novel bit-wise computing unit designed to minimize the critical path and improve the throughput.BitL dynamically switches between horizontal and vertical data lookups across sub-tiles during Multiply-Accumulate (MAC) operations.Additionally, it presents an innovative optimization technique to maximize the utilization of computing units while switching its lookup direction.Our evaluation demonstrates that BitL delivers up to 1.92× higher throughput compared to a baseline DNN accelerator and achieves a 1.24× improvement over recent zero-bit skipping accelerators.Furthermore, BitL improves energy efficiency by 2.06× on average, with a silicon area overhead of only 5.71%. Seunghyun Lee 0003, Dongho Ha, Sungbin Kim, Sungwoo Kim 0003, Hyunwuk Lee, Won Woo Ro |
MICRO | 1 |