Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Abdullah Yesil

dblp:23/8798 · DBLP profile ↗
← Back
1ranked-venue papers
1as first author
0since 2021 · last 2019
0000-0002-0607-8226ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits
0.412019
Design and Experimental Evolution of Memristor With Only One VDTA and One Capacitor · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019
Integrated circuit design › analog and mixed-signal circuits
memristor emulator
0.412019
Design and Experimental Evolution of Memristor With Only One VDTA and One Capacitor · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019

Methods — techniques the papers use, named apart from their topics

cadence simulation · 0.4VDTA · 0.4
YearPublicationVenuePosition
2019 Design and Experimental Evolution of Memristor With Only One VDTA and One Capacitor
abstract
In this paper, we present a memristor emulator based on voltage difference transconductance amplifier (VDTA). The proposed memristor emulator circuit contains only one VDTA as an active element and single grounded capacitor which benefits from the integrated circuit. Furthermore, it can be utilized MOS-capacitance instead of the external capacitor in the circuit. The complete memristor emulator is laid by using Cadence Environment using TSMC 0.18 μm process parameters. It occupies an area of 35.7 μm × 29 μm. Its simulation results are given to demonstrate the performance of the presented memristor emulator in different operating frequencies, process corner, and radical temperature changes. Moreover, prototype circuit is implemented to confirm the theoretical analysis by employing the single LM13700 commercial device as an active element. Experimental results of the designed memristor emulator are given to investigate its ability for different operating frequencies, the capacitance value and resistor value and DC supply voltage. The experimental results are in accordance with theoretical analyses and simulation results.
Abdullah Yesil, Yunus Babacan, Firat Kaçar
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1