There is growing interest in developing non-invasive, widely accessible screening approaches for coronary artery disease (CAD) that are compatible with wearable technology. Prior studies have examined the association of CAD with abnormalities in the QRS-T and PR segments of the electrocardiogram (ECG), which require accurate identification of the onsets and offsets of P-QRS-T waves. This study proposes an alternative approach that extracts variability features from interval time series defined solely by ECG P-QRS-T wave peaks, thereby overcoming the persistent challenge of precise onset and offset detection. The proposed supervised hybrid feature selection approach identified an optimal feature combination that achieved$\mathbf{9 2 \%}$CAD/NonCAD classification accuracy on the validation dataset. It surpassed popular feature selection algorithms, including LASSO, mRMR, BBA, BCS, and BGW. On a blind test dataset, the selected features enabled the final trained ensemble classifier to achieve 88 % accuracy, correctly identifying 86 % of subjects with CAD and 92% of subjects without CAD-outperforming state-of-the-art methods evaluated on the same dataset. Furthermore, validation on a manually annotated QT database revealed notable correlations between proposed features extracted from peak based and clinically relevant interval time series, supporting their potential interchangeability when automated onset-offset detection is unreliable.

This paper presents a single-inductor, multiple-output (SIMO) DC-DC converter suitable for the micro-battery-powered IoT (Internet-of-Things) applications operating with a very low activity factor. Targeting an average output power of few$\mu $W with a peak output power requirement of a few mW in each output channel, the proposed converter transfers constant-charge to its outputs in a complete switching cycle. Multiple IoT nodes are serviced in a time-division multiplexing under discontinuous conduction mode (DCM) of operation for minimizing the cross-regulation issue. An internal priority sequencing logic ensures reliable power-up sequencing during startup. Additionally, the proposed SIMO converter offers an inherent soft-start mechanism, effectively mitigating current-stress on power MOSFETs. Also, the features of priority-based servicing under dynamic conditions, resolve a conflict when catering to multiple outputs at the same instant. The design is highly scalable towards meeting the increased load demand. Implemented in a standard 180 nm CMOS technology, the proposed converter generates three outputs (0.9 V, 1.2 V and 1.5 V) with a maximum load current of 5 mA simultaneously in each of the output channels. Using a single inductor of$10~\mu \text{H}$and an output capacitor of$10~\mu \text{F}$in each of the outputs, the proposed converter shows an output ripple < 22 mV with a peak power efficiency of 91.73%.

Coherence between the parasympathetic (PNS) and sympathetic (SNS) nervous systems is essential for regulating the intrinsic physiologic processes of the autonomic nervous system. This paper proposes a Granger causality (GC)-based ad-hoc statistical framework to analyze the causality between the PNS and SNS response for affective computing tasks. Our study employs vector autoregression modeling of heart rate variability and galvanic skin response signals, pre-processed with physiologically inspired assumptions in a specific frequency range. Publicly available datasets of experiments designed with varying difficulty stressors are used for experimental evaluation. The dataset includes six psychological tasks and n-back tests on a personal computer, encompassing cognitive load and cognitive capacity tasks. The GC test’s statistical significance highlights the possible causal relationship between PNS and SNS for varying time lags and task difficulty levels. Besides, SNS and vagal tone (PNS) influence the perceived multidimensional workload, causating multifaceted aspects of performance.

Charge equalization is essential to maximizing the performance and functionality of lithium-ion battery packs. Various equalization topologies have been developed using charge equalization circuits (CEC) integrated within the Battery Man-agement System (BMS). However, when implemented using buck-boost CEC with conventional switching operations, the adjacent cell-to-cell ($AC2C$) topology exhibits the maximum equalization loss. Therefore, a maximum-minimum equalization algorithm is proposed to control the cell current by regulating the control input of the CEC, which will improve the efficiency of the equalization operation. In this work, two types of CECs, namely buck-boost and dual half-bridge, have been investigated for the series AC2C equalization topology, and a comparison study between CECs in terms of per-unit development cost, equalization efficiency, and time for different control approaches has been pre-sented. The detailed mathematical modeling for each CEC type is formulated to replicate the identical equalization operation. The proposed methodology is validated with$a$48 V, 20 Ah battery pack developed in the PLECS simulation environment.

Atrial fibrillation (AF), the most frequent type of cardiac arrhythmia, has no apparent clinical symptoms in most cases for patients, making it more challenging to diagnose. However, the alterations in regular heart rhythm with an absence of visible P-waves in an Electrocardiogram (ECG) are often characterized as AF symptoms. ECG signals are often employed for AF prognosis to minimize the risk of stroke, coronary artery disease, and other cardiovascular diseases. This work proposes a new vision transformer (ViT) variant, namely, Dilated Residual ViT (DiResViT), by replacing the original patchify stem in ViT with dilated convolutional stem having residual connections for improved AF detection from an ensemble of ECG time-frequency representations. Dilated convolutions facilitate dense feature representation by comprehending the multi-scale contextual information and allowing the receptive field to expand exponentially without losing resolution. The introduction of residual connections alleviates the vanishing and exploding gradients problem by enabling the gradients to bypass some of the non-linear activation functions with improved training convergence. DiResViT’s exhaustive experimental validation outperforms the prior art in ECG-based AF detection, while the ablation study evinces enhanced performance compared to the existing ViT.

Standard pre-trained convolutional neural networks are deployed on different task-specific limited class applications. These applications require classifying images of a much smaller subset of classes than that of the original large domain dataset on which the network is pre-trained. Therefore, a computationally inefficient and over-represented network is obtained. Hierarchically Self Decomposing CNN (HSD-CNN) addresses this issue by dissecting the network into sub-networks in an automated hierarchical fashion such that each sub-network is useful for classifying images of closely related classes. However, visual similarities are not always well-aligned with the semantic understanding of humans. In this paper, we propose a method that aids the pre-trained network to learn the hierarchy of classes derived from standard taxonomy, WordNet and, produce sub-networks corresponding to semantically meaningful classes upon decomposition. Experimental results show that the cluster of classes obtained for each sub-network is semantically closer according to WordNet hierarchy without degradation in overall accuracy.

The recent works in tensor decomposition of convolutional neural networks have paid little attention to finetuning the decomposed models more effectively. We propose to improve the accuracy as well as the adversarial robustness of decomposed networks over existing noniterative methods by distilling knowledge from the computationally intensive undecomposed (teacher) model to the decomposed (student) model. Through a series of experiments, we demonstrate the effectiveness of knowledge distillation with different loss functions and compare it to the existing fine-tuning strategy of minimizing crossentropy loss with ground truth labels. Finally, we conclude that the student networks obtained by the proposed approach are superior not only in terms of accuracy but also adversarial robustness, which is often compromised in the existing methods.

The traditional body of literature on analog testing deals with propagation of faults to the output nets of the circuit. Often the set of detectable faults remains unsatisfactory because suitable stimuli cannot be found for propagating certain faults to the output. Existing technology supports capturing of the state of internal nets of a circuit, thereby enhancing the scope of detecting faults by observing their effect on internal nets. This approach is feasible only if the number of internal nets probed by the built-in test structure is very few. This paper presents a structured approach that identifies the sensitive nets, namely a well chosen small subset of internal nets that are affected by these faults. We utilize the speed of DC analysis and some common behavioral aspects of analog signals to find out this subset. We report dramatic improvement in fault coverage on several circuits including benchmarks.

Detection of faults in a mixed-signal SOC at the pre-silicon stage is a challenge, especially when it has substantial analog components. Given the time taken for simulating analog circuits, designing tests to detect faults in them is not a straightforward task. Achieving a high fault coverage without doing extensive time-consuming transient simulation of the circuit under test (CUT) has remained elusive in the analog and mixed-signal (AMS) domain. Unlike test generation approach for digital designs which leverage logical equivalence between faults, in analog circuits, there does not exist any notion of logical equivalence, and therefore each fault needs to be treated independently. In this paper, we propose to use a combination of DC operating point analysis and AC analysis of the CUT to identify equivalent faults in analog circuits. We also put forward a methodology of synthesizing inputs which will be able to detect the faults during post-silicon testing. Our studies reveal the effectiveness of this approach in identifying equivalent faults and achieving high fault coverage with considerably reduced computations. By using proposed methodology of fault classification and input signal synthesis, we have been able to achieve a high fault coverage where most of the detectable faults are successfully covered.

We present the Fitness Based Layer Rank Selection (FLRS) Algorithm for Accelerating Convolutional Neural Networks by CANDECOMP/PARAFAC (CP) Decompositions. FLRS selects the layers and corresponding ranks based on a parameter fitness factor. The advantage of the proposed FLRS algorithm is that it does not require retraining iteratively during rank selection. The experimental results show that VGG-16 Network can be replaced by an approximate network where the convolutional layers are replaced by a sequence of four convolutional layers with smaller kernels. The approximated network has less than one-fifth of the original model parameters and performs less than one-fifth of the total number of computations as compared to the original model with an accuracy drop of less than 1% across SVHN, CIFAR-10 and CALTECH-101 datasets.

This paper presents the design of an onboard integrated charger using cascaded converters and cell bypass balancing circuit for lithium-ion battery packs. Lithium-ion based serially connected battery cells experience imbalance in operation while charging and discharging. This limits the effective capacity utilization of the battery pack. Among all the active balancing circuits, cell/module bypass reconfiguration is considered to be quite efficient and fast, but introduces surge currents and reduces the system efficiency. This may also damage the components connected and reduce the battery life. In this paper we propose a modified circuit topology to overcome this problem. Simulations are carried out for 14 series connected cells each with nominal voltage of 3.7 V and capacity of 40Ahr. The results indicate considerable scope of application of the proposed approach for on-board electric vehicle applications.

Quantization issues have fundamental bearings on regulation and transient behavior of digitally controlled DC-DC converters. Further, the inherent nonlinearities of quantization may lead to nonlinear oscillations. Usually, the methods to address these oscillations are either resource-intensive, or employ techniques which degrade transient and/or steady-state performance. In this work, we evaluate the limitations of the two widely-used ADC quantization schemes with respect to these aspects, and propose a new dynamic type of quantization, which mitigates the problem of nonlinear oscillations while maintaining or even improving the regulator performance. The results of the proposed scheme are compared against the prior art and are experimentally validated.

Single-stage regulator topologies are often preferred in embedded applications due to their low power consumption with a single-pole behavior, resulting in easy frequency compensation. Since the achievable differential gain from a single stage is low, the dc load regulation is poor over a wide dynamic range. This paper presents a single-stage, adaptively biased, low-dropout regulator to achieve a comparable dc load regulation similar to multistage topologies. This is achieved mainly by modifying the adaptive bias loop which amplifies both the common-mode and differential-mode signals. In addition, as the proposed regulator is stable for a wide range of output capacitors, including the capacitor-less (on-chip) and with-capacitor (off-chip) conditions, it is suitable for more generic applications. The proposed regulator is implemented in a standard 0.18-μm CMOS technology. The experimental results show that the regulator is capable of delivering up to 100 mA with a dc load regulation of 0.140 mV/mA and is stable with Co≤3.3 nF (capacitor-less) and Co≥1 μF (with-capacitor).

This paper presents a new concept for an effective design of quadrature band-pass ΣΔ modulators with built-in Signal Transfer Function (STF) filtering action and discusses the architectural level implementation issues for second and third order modulators based on delay line topologies. The methodology uses an architecture which locks the intermediate frequency (IF) to the sampling frequency for both STF and Noise Transfer Function (NTF). Robustness of the structure against the mismatch is analyzed with interference tones placed in different locations of the receiver spectrum, including the image band. Simulations at the behavioral level verify the architecture implementation and the effectiveness of the approach.

This paper presents a technique to study and estimate the dc performance of lateral power MOSFET switches used in on-chip dc-dc converters. The dc performance is characterized by the on-resistance and current distribution profile in the switch layout. In the proposed approach, a netlist is generated that consists of the parasitic resistances extracted from the metal interconnects along with the MOS device fingers present in the layout. This approach is modular and exploits repetitive patterns of power MOSFET layouts to expedite the extraction process. The extracted resistance values are computed from the geometrical and technological parameters of the metal polygons without the requirement of solving complex electromagnetic (EM) field equations. Comparison of results with an industry standard EM solver tool as well as experimental measurements amply demonstrates the computational efficiency and accuracy of the approach.

In our earlier work, we showed that the discrete-time model of a dc-dc converter governed by a pulse skipping modulation (PSM), could be modeled as a discontinuous map, comprising either 1-D functions only or a combination of 1-D and 2-D functions. In this paper, we show that the entire map can be restricted to one dimension for a wide range of parameters. As a parameter is varied, the periodicity of the output waveform may change either monotonically or non-monotonically depending on the character of the voltage mode control loop. Although the map in the right compartment is always stable, the slope of the left compartment may be greater than one for a range of control parameters, which may lead to chaos.

This paper presents the extensions and experimental validations of a new approach recently developed by the authors for accurate estimation of on-resistance (RDS(on)) of large lateral power MOSFET switch layouts present in on-chip DC-DC converters. This approach exploits the highly symmetric and repetitive patterns of power MOSFET layouts to generate the extracted resistance netlist efficiently resulting significant speed up in resistance extraction process. The extracted resistance values in the interconnects are computed from the metal geometry using models that relate resistance values to the geometric parameters of the layout. Comparison of results with an industry standard EM solver tool as well as experimental measurements for power MOSFET layouts of W/L ratio 105amply demonstrate the computational efficiency and accuracy of the approach establishing its applicability for industrial on-chip power array implementations.

This paper presents the concept of a voltage controlled pulse skipping modulation (VCPSM) in a dc-dc converter, which improves the efficiency, ripple magnitude, and transient response over a wide range of light load condition. The duty ratio of VCPSM, instead of remaining constant as in a classical PSM, is controlled using the voltage mode control with an additional input voltage feed-forward along with an adjustable voltage. Because of the synchronization with the external clock, it facilitates the design of the input filter with reduced EMI problems. The sampled data model, averaged small signal model, and average power loss model are obtained to analyze the stability, dynamic performance, and efficiency, respectively. The simulation results are presented to compare the performance of VCPSM with its classical counterpart. Because of the absence of the any current sensing circuit, VCPSM may be useful for improving light load performance of high frequency power management ICs.

Estimation of resistance of power devices has become critical for improving the efficiency of on-chip power-management circuits. In this paper, we present an efficient technique for estimation of resistance of a large lateral power-array layout along with parasitics. We extract a resistive network for metalizations utilizing the finite-element method. The method primarily benefits in terms of computational speed from reuse methodology facilitated by repetitive structure of the metal interconnect layers. Device channels are modeled by linear resistances as the power MOS operates mostly in the linear region. Since we avoid use of heuristic-based lumped models or extrapolation techniques for resistance modeling, a good level of accuracy is achieved.

A digital processor capable of computing several two dimensional Position Rotation and Scale Invariant (PRSI) transforms on 64 times 64 pixel images is presented. The architecture is programmable to achieve the following five transforms: Two Dimensional (2D) Fast Fourier Transform (FFT), 2D Log Polar Transform (LPT), 2D Fourier Mellin Transform (FMT), 2D Analytical Fourier Mellin Transform and Phase only Correlation (POC). 1D FFT design with scale and word-length issues is also detailed. Thirty two 1-Dimensional FFTs have been reused as processing elements in the 2-Dimensional FFT unit. Scheme for matrix transpose in O(N) time is also described. The Image Processor has a word length of 16 bits each for real and imaginary parts and has been implemented on Xilinx Virtex II FPGA. It is capable of processing an image in less than 0.1 ms.

Standard wireless communication circuits extensively use bandpass Gm-C filters, whose Total Harmonic Distortion (THD) and Intermodulation Distortion (IMD) have been estimated and modeled previously. However previous approaches have considered only third order nonlinearity effects assuming fully balanced OTAs. This assumption does not hold good for practical circuits. Hence a structural modeling approach which takes into consideration all perceptible orders of nonlinearity has been proposed. The proposed approach abstracts the nonlinear elements from the Gm-C filter and models them using a macro-modeling technique. Results from the proposed model are found to be in good agreement with a designed weakly nonlinear Gm-C filter with a 4 times improvement in simulation time. Extension of the approach to the case of a lossy integrator shows improved accuracy over existing modeling approaches.

A novel current mode control of tri-state boost converter is proposed, which eliminates the zero in the right- half plane and improves the dynamic performance. The tri- state boost converter contains an additional switch across the inductor. Within a clock cycle, the inductor current first rises during the on interval of the main switch, then falls during the off or capacitor charging interval, and finally remains constant during the freewheeling interval when the second switch is turned on. In the proposed controller, the peak value of the inductor current is controlled by peak current mode control whereas the freewheeling current is dependent on the reference voltage. The direct control of the inductor current results in a larger bandwidth due to the fast inner loop and thereby a superior dynamic performance is obtained. The latter is established by comparison with that of voltage mode and current mode controlled classical boost converters which suffer from the RHP zero problem, as well as with other tri-state boost converter control techniques like the constant charging interval and dual mode control.

This paper presents an efficient layout-level synthesis approach for RF planar on-chip spiral inductors. A spiral inductor is modeled using artificial neural networks in which the layout design parameters, namely, spiral outer diameter, number of turns, width of metal traces, and metal spacing, are taken as input. Inductance, quality factor (Q), and self-resonance frequency (SRF) form the output of the neural model. Particle-swarm optimization is used to explore the layout space to achieve a given target inductance meeting the SRF and other constraints. Our synthesis approach provides multiple sets of layout parameters that help a designer in the tradeoff analysis between conflicting objectives, such as area, Q, and SRF for a target-inductance value. We present several synthesis results which show good accuracy with respect to full-wave electromagnetic (EM) simulations. Since the proposed procedure does not require an EM simulation in the synthesis loop, it substantially reduces the cycle time in RF-circuit design optimization.

This paper presents an exploration procedure for mapping given functional specifications of an analog system to the specification parameters of individual component blocks of the system topology. A meet-in-the-middle approach has been followed for constructing the feasible design space. It is constructed as the intersection of an application-bounded specification space and a circuit-realizable specification space. The least squares support vector machine principle is used to accurately identify the actual geometry of the feasible design space. The reduced design space speeds up the exploration procedure. The benefit of our methodology is the ability to obtain practically correct circuit-level specifications of the component blocks of the system in a single pass. The effectiveness of the procedure has been demonstrated by considering a complete system. The simulation results satisfy the desired specifications of the system, validating the overall procedure.

Typical analog and radio frequency (RF) circuit sizing optimization problems are computationally hard and require the handling of several conflicting cost criteria. Many researchers have used sequential stochastic refinement methods to solve them, where the different cost criteria can either be combined into a single-objective function to find a unique solution, or they can be handled by multiobjective optimization methods to produce tradeoff solutions on the Pareto front. This paper presents a method for solving the problem by the former approach. We propose a systematic method for incorporating the tradeoff wisdom inspired by the circuit domain knowledge in the formulation of the composite cost function. Key issues have been identified and the problem has been divided into two parts: a) normalization of objective functions and b) assignment of weights to objectives in the cost function. A nonlinear, parameterized normalization strategy has been proposed and has been shown to be better than traditional linear normalization functions. Further, the designers' problem specific knowledge is assembled in the form of a partially ordered set, which is used to construct a hierarchical cost graph for the problem. The scalar cost function is calculated based on this graph. Adaptive mechanisms have been introduced to dynamically change the structure of the graph to improve the chances of reaching the near-optimal solution. A correlated double sampling offset-compensated switched capacitor analog integrator circuit and an RF low-noise amplifier in an industry-standard 0.18mum CMOS technology have been chosen for experimental study. Optimization results have been shown for both the traditional and the proposed methods. The results show significant improvement in both the chosen design problems

The sensitivity of the response of an analog system to circuit parameter variations is a vital performance metric for evaluation of its quality. This paper proposes a unified high level synthesis methodology for higher order continuous time state variable filters, considering the optimization of this metric. Minimization of the hardware count, which is another important issue, has also been taken into account at a much earlier stage of design. The entire methodology is illustrated with the case study of a state variable low pass filter and the benefits of the approach are clearly brought out.

This paper proposes a novel high level synthesis methodology for optimal linear analog systems in a formal and systematic way. It takes as an input, a high level description as well as the desired specifications of the system and gives as an output, an optimal sized architecture as well as certain constraints. This facilitates hierarchical analog system design and reduces circuit designers' effort by providing block level sizes with appropriate tolerance level. The methodology defines an abstract description of the system, selects an optimal architecture by exploring the entire architecture space and finally performs a behavioral sizing of the architecture. The entire methodology is illustrated with the case study of a state variable filter and the benefits of the approach are clearly brought out.

This paper presents a multi-objective evolutionary algorithm based approach to yield-inclusive design space exploration of analog circuits. The yield objective function is included from the beginning in the optimization cycle, and is estimated economically by support vector regression models built from training data provided by the optimization process itself. We propose techniques to effectively handle the inaccurate nature of model-based yield estimates through various stages of the optimization process, and a two-level hybrid algorithm to keep the modeling cost reasonable. The experimental results presented for two real-world circuit examples look encouraging and show the effectiveness of the proposed method in providing designers with multiple trade-off choices

This work is concerned with the development of generic, non-intrusive and flexible algorithms for the design of digital circuits with on line testing (OLT) capability. Most of the works presented in the literature on OLT have used single stuck at fault models. However, in deep submicron era single s-a fault models may not capture more than a fraction of the real defects. To cater to the problem it is now advocated that additional fault models such as Bridging faults, Transition faults, Delay faults etc. are also used. The proposed technique is one of the first works that enables on-line detection of bridging faults and provides a high value of n for the n-Detect tests. The technique can handle generic digital circuits with cell count as high as 15,000 and having the order of 2500 states. Results for design of on-line detectors for various ISCAS89 benchmark circuits are provided. The results illustrate that with marginal increase in area overhead, if compared to ones with single s-a fault coverage, the proposed scheme also provides coverage for bridging faults and high value of n for n-Detect coverage.

The knowledge of optimal design space boundaries of component circuits can be extremely useful in making good subsystem-level design decisions which are aware of the parasitics and other second-order circuit-level details. However, direct application of popular multi-objective genetic optimization algorithms were found to produce Pareto fronts with poor diversity for analog circuit problems. The paper proposes a novel approach to control the diversity of solutions by partitioning the solution space, using local competition to promote diversity and global competition for convergence, and by controlling the proportion of these two mechanisms by a simulated annealing based formulation. The algorithm was applied to extract numerical results on analog switched capacitor integrator circuits with a wide range of tight specifications. The results are found to be significantly better than traditional GA based uncontrolled optimization methods.

We propose a wide-band model of spiral inductor in which a resistance is incorporated in series with the overlap capacitance that estimates the underpass oxide leakage and a parallel combination of lateral substrate resistance and capacitance is introduced to model the lateral substrate coupling at high frequencies. The particle swarm optimization (PSO) algorithm is used for the extraction of the model parameters. The proposed model has been verified with the measured data of octagonal spiral inductors fabricated on a six-metal BiCMOS7 process. The model along with the PSO extraction procedure gives excellent fit when compared with the measured data over the frequency range up to 10GHz. The frequency independent elements of the model facilitate it to be integrated in a SPICE-compatible simulator.

This work is concerned with the development of algorithms and CAD tools for the design of digital circuits with on line monitoring capability. An existing theory of fault detection and diagnosis available in the literature on discrete event systems has been adopted for on-line detection of stuck-at faults in digital circuits. Efficient computational techniques to deal with very large state spaces based on ordered binary decision diagrams and abstraction have been proposed. Based on these a CAD tool has been developed that can provide a fully automated flow for design of circuits with on-line test capability without the requirement of any modification to the core and can handle generic digital circuits with cell count as high as 15,000 and having the order of 2/sup 500/ states. Chips, designed using this methodology have been fabricated in 0.18-micron technology and are tested to be working.