Weather Monitoring Systems available in the market are typically closed systems that are designed to work only with other equipment from the same manufacturer. This hinders the collection of information from a variety of weather stations, preventing denser data collection and better observation of weather patterns through collaborative weather sensing among individuals and institutions. We leveraged the programmability of software-defined radios (SDRs) to enable collecting data from multiple, heterogeneous weather stations by a single radio. We developed a weather station gateway equipped with SDRs that are programmed to receive and decode information from weather stations that use different protocols and operate at distinct frequencies. Data from these stations are stored both locally and online, with update intervals being real-time for the local storage and every 15 minutes for the online database. Deployment results show reliable data reception from the heterogeneous weather stations over a 24-hour period.

As the world becomes increasingly urbanized and industrialized, the quality of air has become a critical concern for public health. Consequently, various studies involving indoor and outdoor air quality monitoring have emerged and identified airflow as one of the main factors. Even though airflow was deemed a major influence in the dispersion and concentration of pollutants, existing monitoring systems does not consider it when gathering data. To address this issue, the study focused on designing a wireless sensor network for indoor-outdoor air quality and dispersion assessment which can be deployed in different facilities and buildings. This was accomplished through air quality sensors and anemometers which were utilized for measuring pollutants levels, wind speed, and direction. The air quality data of each sensor node were measured and sent to the database server together with the anemometer data. The monitoring system successfully collected air quality levels and wind speed data. Results showed that air flow is a factor in the air quality of a facility. Furthermore, the outdoor environment indicated a worse air quality index in comparison to the indoor environment primarily due to its exposure to more environmental elements. The proposed infrastructure can serve as a stepping stone in the development of a smart building management system.

Environmental monitoring applications often employ an RT-PCR assay step in their methodologies, and often collect samples in the field, far away from a laboratory. In this setting, such fieldwork would benefit greatly from a device that can carry out the reaction. This project involved the construction of a custom RT-PCR thermocycler based on OpenPCR's open source design with the objective of portability, achieved through battery operation. Design changes were made to both scale back the power consumption of the device to 50W, while managing the tradeoffs that come with this miniaturization in order to achieve battery powered operation. A heating element was introduced to improve temperature ramp rate performance, alongside a custom power module to facilitate battery operations. Portability is supplemented by LCD-keypad standalone user interfacing, alongside logging and real time clock features for user accessibility.

Audio-based health monitoring systems have gained traction for its capability in capturing different physiological target signals and holding features relevant in diagnosis and treatment, making it a feasible form of data acquisition in biomedical signal processing and feature extraction. Acquiring audio for both heart and respiratory sounds for rate estimation was accomplished using the bottom microphone of the Google Pixel 6A from the trachea and anterior left. A direct comparison of the filter-Hilbert and wavelet-Shannon algorithms based on literature with modifications catering to the application of this study was done to measure their performance and reliability against the KardiaMobile 6L EKG. Tests done were able to show good accuracy for both algorithms on heart rate calculations on both the trachea and anterior left, satisfying having less than ± 10 BPM difference from control. Tests for respiratory rate only provided promising results of less than ± 5 CPM difference from control for tracheal recordings,

This study contributes to improving heart rate (HR) monitoring by comparing the Peripheral Beat Amplitude (PBA) and Smoothed Z-score Peak Detection (Z-Score) algorithms for HR extraction across different body sites. The Z-Score algorithm, leveraging on edge computing, demonstrated higher accuracy than PBA, with a Mean Absolute Error (MAE) around 4 BPM. The study also explores the suitability of the Perfusion Ratio technique for Blood Oxygen (SpO2) levels and the Welch method for respiratory rate (RR). Testing was conducted simultaneously at four distinct body sites (finger, wrist, arm, and ankle) during sitting and walking activities on six healthy individuals. Results indicate that the wrist is the optimal measurement site for various physiological parameters. Post-processing techniques were deliberately chosen to enhance the system's overall performance. The focus on HR necessitated evaluating two algorithms, given its critical importance. For SpO2and RR, single algorithms were selected to streamline processing while ensuring reliable measurements. The developed system exhibits acceptable power consumption of 51.98 m W and achieves an average coverage of 80% in controlled tests, indicating a significant portion of monitoring time provides accurate physiological data. This study emphasizes the deliberate selection of algorithms and measurement sites, demonstrating the superiority of the Z-Score algorithm and the practicality of integrating HR, SpO2, RR, and PPG monitoring in a single system.

A method for extracting lettuce phenotypic features using an ARTY A7-35T FPGA platform is proposed. Image acquisition is done by interfacing an OV7670 CMOS camera with FPGA and saving image data on DDR3 memory. The image processing techniques firstly involve color model conversion for saturation enhancement. Then, binarization is done as an initial step in background discrimination, using a threshold value on the green channel of image. To construct a solid figure for foreground, morphological transformations are implemented. Then, pixel count of foreground white pixels are used as an argument in the computation of lettuce canopy area. The FPGA implementation consumes 85.89% of total LUTs resources of the chosen FPGA board with errors as low as 1.28% on the computed canopy area value compared with a MATLAB benchmark. Power consumption reached up to 1.73W, with a total calculated latency of 596.51 ms from image acquisition to canopy area value.

With the rise of IoT and its many applications, the capabilities of sensor nodes in wireless sensor networks have increased due to the large amounts of sensed data that incur a significant amount of workload at the network core. As such, edge computing applications, which take computing away from the network core into the network edge, become more widely used. This paper presents a pipelined RISC-V RV32IMC processor with interrupt support as a solution to this challenge. For communication with peripherals, the processor supports the protocols I2C, SPI, and UART. Design optimizations, delay balancing and clock gating, resulted in a 13.3% maximum operating frequency increase and a 23.3% reduction in the dynamic power consumption of the core processor. The implemented processor utilizes an average core power of 30.752 mW while operating at a frequency of 50 MHz on a Digilent Arty A7 Board with a Xilinx Artix-7 FPGA.

Security is a concern in wireless sensor networks, which are inherently prone to third party attacks. As such, cryptography is used to make a secure mode of communication among nodes and/or between nodes and base stations. However, conventional algorithms are resource-hungry and therefore not fit for small devices, hence the creation of a new category of cryptography known as Lightweight Cryptographic Algorithms. These algorithms are still continuously being improved to fit in the decreasing sizes of small scale devices like FPGA-based wireless sensor networks. In this study, we quantify the effects of Data Width Reduction, and Round Unrolling on area, and power consumption. These are tested on three lightweight ciphers: LiCi, ANUII, and QTL. Data Width Reduction reduces area by using only a fraction of the original datapath. It was however found to be ineffective for the chosen ciphers, increasing area by 5.64%, 6%, and 9.2% in LiCi, ANUII, and QTL, respectively. Round Unrolling reduces latency which lessens the contribution of static power for each computation. Results show that round unrolling improves power efficiency by 25.97%, 3%, and 14% in LiCi, ANUII, and QTL, respectively. This comes at 299%, 414%, and 52% increase in area. The results allow newer and better lightweight ciphers to be further improved for small scale devices.

Energy consumption is very critical for environmental monitoring using wireless sensor networks, thus, every block must be designed to consume low energy to be within the limited energy budget of a sensor node. In the context of improving the power efficiency of the analog-to-digital converter (ADC), for this specific application, successive approximation register (SAR) ADC is the best architecture to use. In addition, coarse-fine technique has been proven to reduce power consumption in SAR ADCs. However, design considerations involving the coarse ADC bit allocation are important but not discussed in literature. These includes the following: trade off between resolution of the coarse stage and the accuracy of the ADC; trade off between the energy consumption, accuracy and speed of the comparator block; and trade off between energy consumption and accuracy of different switching schemes for the digital-to-analog (DAC) block. This project produced models of these trade-offs, provided a methodology in designing coarse-fine SAR ADCs, implemented two ADCs in the schematic level: the one with the lowest energy consumption; and the one with the highest Schreier figure of merit (FoMs), and implemented the ADC with the lowest energy consumption in the layout level. Optimization using the MATLAB model in the DAC lead to k = 4 which gives the lowest power and k = 3 which gives the highest Schreier FoM. Schematic implementation at 50kSps of k = 4 and k = 3 gave: 2.201pJ and 2.3617pJ switching energy; 9.2 and 9.3 ENOB; and 170.96 dB and 170.72 dB Schreier FoM, respectively. This project was also able to match the trends of the models to the simulations although there are deviations of values. However, ENOBs fall within the target range of ENOBs.

This paper highlights the design and implementation of a thermoelectric energy harvesting interface circuit that generates a regulated 1 V voltage level at the output and delivers the maximum possible energy to a wireless sensor node. The system is able to self-start from a 270 mV input produced by a thermoelectric module that utilizes the varying temperature conditions from the environment. A maximum power point tracking mechanism is included so that the system would always operate at the maximum power point. The whole system is implemented in 65 nm CMOS Process Technology covering an area of 475 um by 360 um.

This paper presents a low-power, low-area, and low complexity capacitance to pulse width (C-to-PWM) converter for capacitive sensors. The designed converter consists of a a clock generator, RC stage, comparator and XOR. The differential nature of the circuit produces square waves with pulse width proportional to the difference of the reference capacitance from the sensing capacitance. Moreover, the matched differential branches makes the output resilient to delays and jitters introduced by the blocks. The designed converter achieves a dynamic range of 1pF - 21.5pF at a sensitivity of 4.03μs/pF. Additionally, it is designed in 65nm CMOS technology and only consumes a maximum power of 256nW from a 1V supply at a frequency of 10.59kHz. The functionality of the circuit and the blocks involved are presented along with measurement results.

Video encoding has different methods and techniques in its implementation. Hardware implementations of video encoding systems are usually limited to a single set of compression techniques because of the trade-offs in area and power consumption. A workaround for this is through reconfigurable hardware devices such as the FPGA. The aim of this work is to use an FPGA to extend the set of compression techniques of an available video encoding system by changing the number of intra-prediction modes and motion estimation algorithm. Additionally, since the base system only caters to intra-prediction, an architectural design for the inter-prediction module with full-pixel resolution has been accomplished. The addition of intra-prediction modes showed a very minimal decrease in the total encoding time. This, however, showed 0.44% increase in the resource utilization. The different search algorithms used manifested the expected highest to lowest execution time respectively. The trade-off of higher PSNR versus longer encoding time was shown. An average of 76.96% decrease in execution time was observed while achieving a 0.27% decrease in PSNR.

Wireless sensor networks for monitoring and sensing applications have grown steadily in recent years. These applications are composed of swarm of sensor nodes within close proximity. Typical nodes have a limited power supply and the communications block usually has the largest percentage in the total power consumption. Current trends are geared towards low power design and to address this, three gain settings on the main data receiver's intermediate frequency stage was incorporated to the system based on the transmitter and receiver distance range of 1 m to 10 m. A wake-up receiver was also integrated with the main data receiver, taking the role of idle listening as the main receiver is in sleep mode. The main receiver has a sensitivity of -50 dBm to -70 dBm and consumes 4.14 mW of power, while the wake-up receiver has a sensitivity of -50 dBm and consumes 13.73 μW of power. An energy efficiency of 4.1 nJ/bit and 138 pJ/bit are achieved by the main and wake-up receivers, respectively. Up to 90% of power savings can be achieved as long as the main receiver duty cycle does not go beyond 96%. The estimated area of the integrated receiver chip layout is 1.634 sq. mm.

This paper presents an ultra-low power wake-up receiver (WuRx) based on direct active-RF detection architecture. A noise-cancelling technique is implemented on the RF envelope detector to minimize the noise due to the circuit components and to obtain a higher signal-to-noise ratio while maintaining its power within tens of microwatts. Compared to other wake-up receivers, this work focused on designing the receiver with reduced system complexity through a single-ended topology and minimized number of circuit components; thus, ultra-low power operation is attained. At 2.4 GHz RF operating frequency, a - 50 dBm sensitivity is achieved with 100 kbps data rate. Power consumption is measured as 13.7 μW from a 1 V supply voltage, obtaining 138 pJ/bit energy efficiency. The prototype receiver was designed using a 65 nm CMOS technology process and has a layout area of 0.194 mm2.

Due to the limited energy supply of wireless sensor nodes, minimizing their power consumption has become a primary concern to increase their battery lives. These sensor nodes require clock signals to process data and to synchronize with other sensor nodes in the network. However, clock generator circuits usually consume a lot of power. This work addresses this problem by implementing a low-power all-digital phase-locked loop (ADPLL) in a 65nm CMOS process with a low operating voltage of 0.5V. Its output frequency range is 0.285 - 48MHz with a power consumption of 8.25μW at 23MHz. With the use of the frequency estimation algorithm, the ADPLL is able to achieve fast lock-in time within 5 reference clock cycles with frequency errors of less than 1.5%.

Recent researches on the development and deployment of large-scale wireless sensor networks focus on the reduction of power consumption to increase network lifetime. This entails the development of more efficient hardware and the integration of the multiple components into a single platform; possibly, a system-on-a-chip sensor node platform. This paper focuses on the application of Q-learning to node clustering as an effective technique in reducing power consumption. A hardware implementation of CLIQUE, a Q-learning-based clustering algorithm that enhances the operation and resiliency of the network and improves the energy expenditure of the sensor nodes, is presented. The power consumption of the hardware is recorded to be around 6.4 mW. By incorporating this value into OMNeT++, it was demonstrated that CLIQUE improves energy expenditure by 6%-19% and extends network lifetime by 5%-22%, when compared to LEACH, a traditional clustering algorithm.

Designing of analog circuits is a very difficult and tedious task even for experienced designers and it becomes complicated even further due to short-channel effects and low voltage supply brought by technology scaling. The emergence of Wireless Sensor Networks (WSNs) only strengthened the need for a faster and more efficient analog design process. The operational amplifier is one of the fundamental blocks for analog circuits and has many applications for different devices. This project presents a tool that will automatically size the components in a CMOS Miller operational amplifier based on the gm/IDmethodology. The tool considers the intended application when handling the trade-offs regarding the characteristics of the amplifier. The considered applications are identified as comparator, filter, and preamplifier. The tool was successful in designing three amplifiers for each application. To further verify the functionality of the tool, a layout of the preamplifier design was created and tested to prove that the design stays within the required specifications.