We propose a three-stage load balancing packet switch and its configuration scheme. The input- and central-stage switches are bufferless crossbars, and the output-stage switches are buffered crossbars. We call this switch ThRee-stage Clos-network swItch with queues at the middle stage and DEtermiNisTic scheduling (TRIDENT), and the switch is cell based. The proposed configuration scheme uses predetermined and periodic interconnection patterns in the input and central modules to load-balance and route traffic, therefore, it has low configuration complexity. The operation of the switch includes a mechanism applied at input and output modules to forward cells in sequence. TRIDENT achieves 100% throughput under uniform and nonuniform admissible traffic with independent and identical distributions (i.i.d.). The switch achieves this high performance using a low-complexity architecture while performing in-sequence forwarding and no central-stage expansion or memory speedup. We analyze the operations the configuration mechanisms perform on the traffic traversing the switch. We use this analysis to prove that the switch achieves 100% through under i.i.d. traffic. We also show that the switch forward cells in-sequence. We present a simulation analysis as a practical demonstration of the switch performance under uniform and nonuniform i.i.d. traffic.

We propose a configuration scheme for a load-balancing Clos-network (LBC) packet switch that has split central modules and buffers in between the split modules. Our split-central-buffered LBC switch is cell-based. The switch has four stages, namely input, central-input, central-output, and output stages. The proposed configuration scheme uses a pre-determined and periodic interconnection pattern in the input and split central modules to load-balance and route traffic. The LBC switch has low configuration complexity. The operation of the switch includes a mechanism applied at input and split-central modules to forward cells in sequence. The switch achieves 100% throughput under uniform and nonuniform admissible traffic with independent and identical distributions (i.i.d.). The switch uses no speedup nor memory expansion. We demonstrate the properties of the switch through traffic and timing analysis.