Recent studies have revealed that laser-based side-channel analysis (SCA) attack methods, particularly optical probing (OP), pose a serious threat to the security of integrated circuits (ICs). State-of-the-art countermeasures focus mainly on approaches in the domain of circuit design to mitigate the OP attack. However, methods to analyze OP, which can be integrated into the tool flow during design time, are scarce. Consequently, the actual robustness against OP can only be evaluated during post-fabrication, which may require a redesign of the IC and result in huge costs. To mitigate the lack of such methods and tools, we introduce OPTI-Sim. OPTI-Sim is an OP analysis framework, enabling designers to explore the circuit’s susceptibility against OP during design time. As OPTI-Sim allows the study of the vulnerability of the circuits against OP attacks prefabrication, it has immense potential to reduce design time and production costs of security-relevant ICs. OPTI-Sim enables an automated OP analysis at the layout level by reading layout files, performing logical computations to retrieve the state of each logic cell in the design, and performing OP analysis. The applicability of OPTI-Sim is explored by designing and evaluating a cell library and exemplary circuits that are robustified against OP attacks. Another feature of the proposed framework discussed in this work is its ability to explore the detection of hardware Trojans (HTs) using OP. HT detection using OP omits the need to have access to the golden chip to expose the HT, and results in a 100% HT detection rate. Furthermore, to the best of our knowledge, OPTI-Sim is the first OP framework of its kind.

Approximate circuits have become ubiquitous in error-resilient applications. These circuits provide large reductions in area, power, and delay at the cost of erroneous computations. The error-resilient applications produce acceptable output quality, even after the introduction of erroneous computations. However, we observed that the error resilience of an application varies widely with respect to the applied inputs. Since prior works have mostly focused on using samples from a uniform distribution while designing the approximate circuits, they are unable to exploit input aware properties to design optimal circuits. Hence, in this work, we bridge this gap and propose Formally Verified Library of Input Data Aware Approximate Circuits (FV-LIDAC). FV-LIDAC is the first formally verified library of input distribution aware approximate arithmetic circuits. We use three of the most widely occurring distributions, namely uniform, normal, and exponential distributions, to show that optimal design sets are heavily dependent on the input data. FV-LIDAC chooses the best designs among millions of functional approximated adder and multiplier circuits, depending upon the inputs. Since there are no existing input-aware approximate circuit libraries, we compared FV-LIDAC against state-of-the-art input-unaware EvoApproxLib, to further highlight the need for FV-LIDAC. Additionally, we perform case studies on real-world applications to further highlight the improvement over state-of-the-art. We aim to make the Pareto-optimal designs available as open source to stimulate further research.

Reconfigurable Field Effect Transistors (RFETs) can be programmed on the fly to behave either as NMOS or PMOS. Digital circuit designs using RFETs have been shown to benefit both in design and security metrics compared to traditional FETs. In this paper, we highlight the problem associated with the cascading of RFET-based logic cells that have their Source(S)/Drain(D) terminals not connected to the supply Voltage(VDD)/Ground(GND). While these circuits occupy a lesser area, there is a drastic increase in the delay of these logic cells when they are cascaded as a result of the S/D being driven by inputs. We then discuss two methods to mitigate this issue using a) buffer insertion for delay minimization, and b) logic cells that have their S/D terminals driven by VDD/GND.

With the exponential increase in the popularity of the RISC-V ecosystem, the security of this platform must be re-evaluated especially for mission-critical and IoT devices. Besides, the insertion of a Hardware Trojan (HT) into a chip after the in-house mask design is outsourced to a chip manufacturer abroad for fabrication is a significant source of concern. Though abundant HT detection methods have been investigated based on side-channel analysis, physical measurements, and functional testing to overcome this problem, there exists stealthy HTs that can hide from detection. This is due to the small overhead of such HTs compared to the whole circuit.

Optical Probing (OP) has been shown to be capable of retrieving intellectual property of the chips. However, to design a robust circuit against OP, the chip must be designed, fabricated, and optically probed in an experimental setup to determine the OP robustness of the design which is time consuming. To mitigate the aforementioned problems, we propose a simulation framework, namely FELOPi, which takes the layout file format of a design as an input and then performs OP on it. FELOPi can help designers to design robust circuits toward OP attacks before fabricating the chip. Hence, utilizing FELOPi results in tremendous time and cost reduction.

Laser-assisted side-channel analysis techniques, such as optical probing (OP), have been shown to pose a severe threat to secure hardware. While several countermeasures have been proposed in the literature, they can either be bypassed by an attacker or require a modification in the transistor's fabrication process, which is costly and complex. In this work, firstly, we propose a formulation for the caliber of reflected light from OP. Secondly, we propose circuit design techniques and logic styles to alleviate OP attacks based on our formulation. Finally, we compare several logic families and circuit design techniques in terms of performance and OP security merits. In this regard, we perform simulations to compare the optical beam interaction between the different logic gates. By utilizing our proposed circuit design techniques and dual-rail logic (DRL), the signal-to-noise ratio (SNR) of the reflected light from OP is reduced significantly.

This paper presents techniques and design structures to reduce the time-multiplexed hardware complexity of a feed-forward artificial neural network (ANN). After the weights of ANN are determined in a training phase, in a post-training stage, initially, the minimum quantization value used to convert the floating-point weights to integers is found. Then, the integer weights related to each neuron are tuned to reduce the hardware complexity in the time-multiplexed design avoiding a loss on the ANN accuracy in hardware. Also, at each layer of ANN, the multiplications of integer weights by an input variable at each time are realized under the shift-adds architecture using a minimum number of adders and subtractors. It is observed that the application of the post-training stage yields a significant reduction in area, latency, and energy consumption on the time-multiplexed designs including multipliers. Moreover, the multiplierless design of ANN whose weights are found in the post-training stage leads to a further reduction in area and energy consumption, increasing the latency slightly.

In reversible circuits, a fault as a change in logic value at a circuit node always alters an output logic value, so observability of faults at the output is 100%. In other words, reversible circuits are latent-fault-free. Our motivation is to incorporate this unique feature of reversible circuits to design CMOS circuits having perfect or 100% Concurrent Error Detection (CED). For this purpose we propose a new, fault preservative, and reversible gate library called Even Target - Mixed Polarity Multiple Control Toffoli (ET-MPMCT). By using ET-MPCT, we ensure that the parity, even or odd, is preserved at all levels including the output level unless there is a faulty node. Our design strategy has two steps for a reversible function: 1) implement the reversible functions with the ET-MPMCT library; and 2) apply reversible-to-CMOS gate conversion. In case an irreversible function needs to be synthesized then its reversible form is used followed by the two design steps. As a result, we have come up with a CMOS circuit having 100% CED. The performance of our approach is compared with other CED schemes in the literature in terms of area, detection rate, and power consumption. Simulations are done with Cadence Genus tool using TSMC 0.18 μm technology. Clearly, results are in favor of our proposed technique.