Chi-Jui Chen

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VLDB 2026 Research / reviewers in the wild / expert

dblp:232/7762 · DBLP profile ↗

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2ranked-venue papers

1as first author

2since 2021 · last 2026

—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems 1 paper		Hardware accelerators and domain-specific architectures · 77% Reconfigurable computing and FPGAs · 23%
Artificial intelligence 1 paper		Efficient and distributed learning · 100%

Topics — the 2 heaviest of 3, each with the papers that count most for it

Topic	Weight	Papers	Last	Evidence papers
Machine learning › Efficient and distributed learning model quantization	0.9	1	2025	BAQET: BRAM-aware Quantization for Efficient Transformer Inference via Stream-based Architecture on an FPGA · FPGA 2025
Hardware accelerators and domain-specific architectures › machine learning accelerator › transformer accelerator transformer inference accelerator	0.9	1	2025	BAQET: BRAM-aware Quantization for Efficient Transformer Inference via Stream-based Architecture on an FPGA · FPGA 2025

Methods — techniques the papers use, named apart from their topics

simulated annealing · 1.7high-level synthesis · 1.7flashattention · 1.7

Year	Publication	Venue	Position
2026	Switchable-Precision Universally Slimmable Networks Chi-Jui Chen, Edwin Arkel Rios, Bo-Cheng Lai	IEEE Signal Process. Lett.	1
2025	BAQET: BRAM-aware Quantization for Efficient Transformer Inference via Stream-based Architecture on an FPGA abstract FPGAs are a compelling substrate for supporting machine learning inference. Tools such as High-Level Synthesis and hls4ml can shorten the development cycle for deploying ML algorithms on FPGAs, but can struggle to handle the large on-chip storage needed for many of these models. In particular the high BRAM usage found in many of these flows can cause Place & Route failures during synthesis. In this paper we propose using a Simulated-Annealing based flow to perform BRAM-aware quantization. This approach trades off inference accuracy with BRAM usage, to provide a high-quality inference engine that still meets on-chip resource constraints. We demonstrate this flow for Transformer-based machine learning algorithms, which include Flash Attention in a Stream-based Dataflow architecture. Our system imposes minimal accuracy drops, yet can reduce BRAM usage by 20%-50%, and improve power efficiency by 264%-812% compared to existing Transformer-based accelerators on FPGAs LingChi Yang, Chi-Jui Chen, Trung Le 0002, Bo-Cheng Lai, Scott Hauck, Shih-Chieh Hsu	FPGA	2