Demo Data from VLDB 2026 / reviewers in the wild / expert
Guanyu Wu
dblp:232/9221
· DBLP profile ↗
3ranked-venue papers
0as first author
3since 2021 · last 2026
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 2 · 2 since 2021Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Storage systems · 100% | |
| Theoretical computer science
1 paper |
Coding theory · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Storage systems › flash and SSD › flash memory › NAND flash
3D NAND flash |
0.8 | 1 | 2024 | Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories · ACM Trans. Archit. Code Optim. 2024 |
Storage systems › flash and SSD
flash memory |
0.8 | 1 | 2024 | Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories · ACM Trans. Archit. Code Optim. 2024 |
Storage systems › flash and SSD › flash memory
LDPC decoding |
0.8 | 1 | 2024 | Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories · ACM Trans. Archit. Code Optim. 2024 |
Coding theory
error-correcting codes |
0.8 | 1 | 2024 | Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories · ACM Trans. Archit. Code Optim. 2024 |
Coding theory › error-correcting codes
LDPC codes |
0.8 | 1 | 2024 | Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories · ACM Trans. Archit. Code Optim. 2024 |
Storage systems
storage reliability |
0.2 | 1 | 2024 | Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories · ACM Trans. Archit. Code Optim. 2024 |
Methods — techniques the papers use, named apart from their topics
threshold voltage distribution modeling · 1.5offsetted read voltage · 1.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Enhancing optimal read voltage prediction for three-dimensional NAND flash memory through data augmentation techniques
Xiangyu Yao, Guanyu Wu, Yina Lv, Jie Zhang 0048, Xinbiao Gan, Qiao Li 0001 |
Eng. Appl. Artif. Intell. | 2 |
| 2024 | Characterizing and Optimizing LDPC Performance on 3D NAND Flash MemoriesabstractWith the development of NAND flash memories’ bit density and stacking technologies, while storage capacity keeps increasing, the issue of reliability becomes increasingly prominent. Low-density parity check (LDPC) code, as a robust error-correcting code, is extensively employed in flash memory. However, when the RBER is prohibitively high, LDPC decoding would introduce long latency. To study how LDPC performs on the latest 3D NAND flash memory, we conduct a comprehensive analysis of LDPC decoding performance using both the theoretically derived threshold voltage distribution model obtained through modeling (Modeling-based method) and the actual voltage distribution collected from on-chip data through testing (Ideal case). Based on LDPC decoding results under various interference conditions, we summarize four findings that can help us gain a better understanding of the characteristics of LDPC decoding in 3D NAND flash memory. Following our characterization, we identify the differences in LDPC decoding performance between the Modeling-based method and the Ideal case. Due to the accuracy of initial probability information, the threshold voltage distribution derived through modeling deviates by certain degrees from the actual threshold voltage distribution. This leads to a performance gap between using the threshold voltage distribution derived from the Modeling-based method and the actual distribution. By observing the abnormal behaviors in the decoding with the Modeling-based method, we introduce an Offsetted Read Voltage (ΔRV) method for optimizing LDPC decoding performance by offsetting the reading voltage in each layer of a flash block. The evaluation results show that our ΔRV method enhances the decoding performance of LDPC on the Modeling-based method by reducing the total number of sensing levels needed for LDPC decoding by 0.67% to 18.92% for different interference conditions on average, under the P/E cycles from 3,000 to 7,000. Qiao Li 0001, Guanyu Wu, Yajuan Du, Xinbiao Gan, Jie Zhang 0048, Zhirong Shen, Jiwu Shu, Chun Jason Xue |
ACM Trans. Archit. Code Optim. | 3 |
| 2022 | CHEF: A Pilot Chinese Dataset for Evidence-Based Fact-CheckingabstractXuming Hu, Zhijiang Guo, GuanYu Wu, Aiwei Liu, Lijie Wen, Philip Yu. Proceedings of the 2022 Conference of the North American Chapter of the Association for Computational Linguistics: Human Language Technologies. 2022. Xuming Hu, Zhijiang Guo, Guanyu Wu, Aiwei Liu, Lijie Wen 0001, Philip S. Yu |
NAACL-HLT | 3 |