Demo Data from VLDB 2026 / reviewers in the wild / expert
Niklas Meyer
dblp:232/9870
· DBLP profile ↗
2ranked-venue papers
0as first author
1since 2021 · last 2022
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 since 2021Artificial intelligence and machine learning · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 70% Integrated circuit design · 23% Hardware accelerators and domain-specific architectures · 7% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
digital circuit design |
0.6 | 1 | 2022 | Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge Application · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Electronic design automation
physical design |
0.6 | 1 | 2022 | Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge Application · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Electronic design automation › physical design
placement and routing |
0.6 | 1 | 2022 | Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge Application · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Electronic design automation › physical design › placement › cell placement
standard cell placement |
0.6 | 1 | 2022 | Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge Application · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Hardware accelerators and domain-specific architectures
edge accelerator |
0.2 | 1 | 2022 | Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge Application · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Methods — techniques the papers use, named apart from their topics
voltage scaling · 0.6presearch scheme · 0.6guided placement and routing · 0.6
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge ApplicationabstractA spectrum of emerging applications, including edge artificial intelligence, advocates the precompute-and-search scheme with embedded small-size content addressable memory (CAM) for its hardware efficiency instead of repetitive arithmetic operations. However, the integration of the CAM macros that are conventionally implemented with full custom analog circuits renders design-space exploration and optimization to be difficult at system level. As an alternative, a complete design flow for compiling ternary CAM on chip using foundry-supplied digital standard cells is introduced in this article. Based on the novel CAM architecture and logic design, we leverage guided placement and routing with mainstream EDA tools for exploiting the inherent structure regularity of CAM-cell arrays in the layout. An analytical model is also presented, which allows us for a systematic investigation on the energy reduction by adapting our design to various presearch structures. Validated on a postlayout$32{\times }64$ternary CAM in 28 nm, our parallel-matching scheme performs at 2.6 GHz with 0.42 fJ/bit/search, and the (8-bit) presearch scheme achieves 0.19 fJ/bit/search at 1.1 GHz, both under the 0.9-V supply voltage. In addition to flexibility for tradeoffs between the search throughput and energy, our all-digital CAM design enables voltage scaling aggressively down to 0.45 V with a minimum energy consumption of 0.06 fJ/bit/search at 50 MHz. Xin Fan 0002, Niklas Meyer, Tobias Gemmeke |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 2018 | Modeling and Trajectory Tracking Control of a New Parallel Flexible Link RobotabstractA completely new compliant lightweight robot is presented with a kinematic loop and a highly flexible link. It is explained how to model such parallel robots accurately but still computationally efficient. The elastic deformations are described with the floating frame of reference approach. For the flexible components this allows to use linear finite element models, which can represent arbitrary geometries. These models are further reduced by modal truncation and a Component Mode Synthesis minimizing the number of elastic degrees of freedom, which is necessary for real-time control purposes. The obtained model of the underactuated robot is non-minimum phase for the end-effector as output. Thus, for the applied trajectory tracking controller which is based on servo constraints, the concept of stable inversion is used. The performance is compared to a relocated minimum phase output. Corresponding simulations are validated by first experimental results showing the need for and high accuracy of the flexible model and the trajectory tracking control. Merlin B. Morlock, Niklas Meyer, Marc-André Pick, Robert Seifried |
IROS | 2 |