The mixed-size placement becomes a great challenge in the modern VLSI design. To handle this problem, the three-stage mixed-size placement methodology is considered as the most suitable approach for a commercial design flow, where the placement prototyping is the most important stage. Since standard cells and macros have to be considered simultaneously in this stage, it is more complicated than the other two stages. To reduce complexity and improve design quality, this paper applies the multilevel framework with a design hierarchy-guided clustering scheme for getting a better coarsening result in order to improve outcome in the following stages. We propose an efficient and effective clustering scheme to group standard cells and macros based on the tree built from their design hierarchies. More importantly, our clustering algorithm considers indirect connectivity between macros which is ignored by previous works. Moreover, we propose a new overlapping bounding box constraint to avoid clustering improper macros which have connections to fixed pins. The experimental results show that wirelength and routability are improved by our methodology.

This paper introduces a routability-driven macro placement algorithm for mixed-size circuits and pays special attention to the effect of regular placement of macros. Once macros are placed with regularity, powerplanning will become easier and better routability can be obtained. Our methodology consists of two stages. First, placement prototyping stage distributes cells and macros over a placement region while keeping those macros and cells with a strong connection and in similar hierarchies tied together. This is facilitated by clustering macros and cells properly in advance. In the second stage, a deterministic macro legalization algorithm is proposed to arrange macros without deteriorating the result obtained in the previous stage. Although several macro legalization algorithms have been proposed in recent years, most of these works adopt the simulated annealing algorithm which usually takes longer runtime. Moreover, they either cannot handle preplaced macros or require preplaced macros to be abutted to chip boundaries. Unlike these approaches, our method iteratively places a macro by extracting available space for it. Experimental results demonstrate the efficiency and effectiveness of our method according to real industry circuits.