Demo Data from VLDB 2026 / reviewers in the wild / expert
Farouk Hebbache
dblp:233/0594
· DBLP profile ↗
3ranked-venue papers
3as first author
0since 2021 · last 2020
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 62% Embedded and real-time systems · 38% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › memory controller
memory arbitration |
0.3 | 1 | 2018 | Shedding the Shackles of Time-Division Multiplexing · RTSS 2018 |
Embedded and real-time systems
worst-case execution time analysis |
0.3 | 1 | 2018 | Shedding the Shackles of Time-Division Multiplexing · RTSS 2018 |
Memory systems
DRAM |
0.1 | 1 | 2018 | Shedding the Shackles of Time-Division Multiplexing · RTSS 2018 |
Memory systems › memory interference
memory bank conflicts |
0.1 | 1 | 2018 | Shedding the Shackles of Time-Division Multiplexing · RTSS 2018 |
Methods — techniques the papers use, named apart from their topics
time-division multiplexing · 0.3slack exploitation · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2020 | Work-conserving dynamic time-division multiplexing for multi-criticality systems
Farouk Hebbache, Florian Brandner, Mathieu Jan, Laurent Pautet |
Real Time Syst. | 1 |
| 2019 | Arbitration-Induced Preemption DelaysabstractThe interactions among concurrent tasks pose a challenge in the design of real-time multi-core systems, where blocking delays that tasks may experience while accessing shared memory have to be taken into consideration. Various memory arbitration schemes have been devised that address these issues, by providing trade-offs between predictability, average-case performance, and analyzability. Time-Division Multiplexing (TDM) is a well-known arbitration scheme due to its simplicity and analyzability. However, it suffers from low resource utilization due to its non-work-conserving nature. We proposed in our recent work dynamic schemes based on TDM, showing work-conserving behavior in practice, while retaining the guarantees of TDM. These approaches have only been evaluated in a restricted setting. Their applicability in a preemptive setting appears problematic, since they may induce long memory blocking times depending on execution history. These blocking delays may induce significant jitter and consequently increase the tasks' response times. This work explores means to manage and, finally, bound these blocking delays. Three different schemes are explored and compared with regard to their analyzability, impact on response-time analysis, implementation complexity, and runtime behavior. Experiments show that the various approaches behave virtually identically at runtime. This allows to retain the approach combining low implementation complexity with analyzability. Farouk Hebbache, Florian Brandner, Mathieu Jan, Laurent Pautet |
ECRTS | 1 |
| 2018 | Shedding the Shackles of Time-Division MultiplexingabstractMulti-core architectures pose many challenges in real-time systems, which arise from contention between concurrent accesses to shared memory. Among the available memory arbitration policies, Time Division Multiplexing (TDM) ensures a predictable behavior by bounding access latencies and guaranteed bandwidth to tasks independently from the other tasks. To do so, TDM guarantees exclusive access to the shared memory in a fixed time window. TDM, however, provides a low resource utilization as it is non-work-conserving. Besides, it is very inefficient for resources having highly variable latencies, such as sharing the access to a DRAM memory. The constant length of a TDM slot is, hence, highly pessimistic and causes an underutilization of the memory. To address these limitations, we present dynamic arbitration schemes that are based on TDM. However, instead of arbitrating at the level of TDM slots, our approach operates at the granularity of clock cycles by exploiting slack time accumulated from preceding requests. This allows the arbiter to reorder memory requests, exploit the actual access latencies of requests, and thus improve memory utilization. We demonstrate that our policies are analyzable as they preserve the guarantees of TDM in the worst case, while our experiments show an improved memory utilization on average. Farouk Hebbache, Mathieu Jan, Florian Brandner, Laurent Pautet |
RTSS | 1 |