Demo Data from VLDB 2026 / reviewers in the wild / expert
David Dlott
dblp:233/8140
· DBLP profile ↗
2ranked-venue papers
0as first author
1since 2021 · last 2025
0009-0004-0384-3086ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 44% Processor architecture and microarchitecture · 44% Energy-efficient computing · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware/software co-design
compiler-architecture co-design |
0.9 | 1 | 2025 | Saving Energy with Per-Variable Bitwidth Speculation · ASPLOS (2) 2025 |
Processor architecture and microarchitecture
speculative execution |
0.9 | 1 | 2025 | Saving Energy with Per-Variable Bitwidth Speculation · ASPLOS (2) 2025 |
Energy-efficient computing
energy-constrained computing |
0.3 | 1 | 2025 | Saving Energy with Per-Variable Bitwidth Speculation · ASPLOS (2) 2025 |
Methods — techniques the papers use, named apart from their topics
hardware speculation · 0.9compiler optimization · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Saving Energy with Per-Variable Bitwidth SpeculationabstractTiny devices have become ubiquitous in people's daily lives. Their applications dictate tight energy budgets, but also require reasonable performance to meet user expectations. To this end, the hardware of tiny devices has been highly optimized, making further optimizations difficult. In this work, we identify a missed opportunity: the bitwidth selection of program variables. Today's compilers directly translate the bitwidth specified in the source code to the binary. However, we observe that most variables do not utilize the full bitwidth specified in the source code for the majority of execution. To leverage this opportunity, we propose BitSpec : a system that performs fine-grained speculation on the bitwidth of program variables. BitSpec is implemented as a compiler-architecture co-design, where the compiler transparently reduces the bitwidth of program variables to their expected needs and the hardware monitors speculative variables, reporting misspeculation to the software, which re-executes at the original bitwidth, ensuring correctness. BitSpec reduces energy consumption by 9.9% on average, up to 28.2% . Tommy McMichen, David Dlott, Panitan Wongse-ammat, Nathan Greiner, Hussain Khajanchi, Russ Joseph, Simone Campanoni |
ASPLOS (2) | 2 |
| 2019 | BeSAT: behavioral SAT-based attack on cyclic logic encryptionabstractCyclic logic encryption is newly proposed in the area of hardware security. It introduces feedback cycles into the circuit to defeat existing logic decryption techniques. To ensure that the circuit is acyclic under the correct key, CycSAT is developed to add the acyclic condition as a CNF formula to the SAT-based attack. However, we found that it is impossible to capture all cycles in any graph with any set of feedback signals as done in the CycSAT algorithm. In this paper, we propose a behavioral SAT-based attack called BeSAT. Be-SAT observes the behavior of the encrypted circuit on top of the structural analysis, so the stateful and oscillatory keys missed by CycSAT can still be blocked. The experimental results show that BeSAT successfully overcomes the drawback of CycSAT. Yuanqi Shen, You Li 0008, Amin Rezaei 0001, Shuyu Kong, David Dlott, Hai Zhou 0001 |
ASP-DAC | 5 |