Password recovery tools are used to recover lost passwords and regain access to precious data. Due to the extremely large time and energy consumption of password recovery, efficient hardware accelerators are demanded to accelerate the recovery process. However, simple and regular data interconnect paths between data sources and non-blocking hash pipelines are hard to construct for Roshal ARchive version 3 (RAR3) algorithm based on field programmable gate array (FPGA) devices. The difficulty comes from the fact that the message format of the hash pipeline inputs vary with the password length and the secure hash algorithm 1 (SHA-1) iteration phase. To attack this problem, a dual-granularity data path adjustment strategy is proposed to eliminate the randomness of message block formats caused by the irregularity of password length and to efficiently schedule the data through the regular data interconnect paths. Experimental results show that the proposed hardware accelerator for RAR3 password recovery is 3.3 × more energy-efficient than a state-of-the-art implementation Hashcat on NVIDIA GTX 1060 GPU.

Password recovery tools are needed to recover lost and forgotten passwords so as to regain access to valuable information. As the process of password recovery can be extremely compute-intensive, hardware accelerators are often needed to expedite the recovery process. This paper thus presents a high performance, energy-efficient accelerator built upon modern hybrid CPU-FPGA SoC devices. The proposed password recovery accelerator relies on the development of a set of intellectual property (IP) cores for implementing variety of encryption algorithms with vastly different characteristics and complexities. To keep the resource requirements of each IP core running on a resource-strapped FPGA to the minimum, while achieving the highest throughput possible, the most performance critical computational hash functions are mapped to the FPGA with two specific optimization techniques, namely the fixed message padding for hashing and loop transformation for deep pipelining. The proposed password recovery accelerator implements a non-blocking deep pipeline design that does not incur any data and structural hazards, which is made possible by applying a task scheduling scheme through the use of block RAMs. Synchronization between tasks that are mapped to run separately on CPU and FPGA is achieved through task reordering and a communication protocol for maximum parallelism and low overhead. The proposed design is evaluated on Xilinx XC7Z030-3 device, and it is compared much favorably with other known implementations. The proposed hardware accelerator design is found 12.5 and 3.1 times more resource-efficient than the pure FPGA-based password recovery accelerators for TrueCrypt and WPA-2, respectively. The proposed implementation also shows more than 200 percent improvement in energy efficiency over a state-of-the-art implementation on NVIDIA GTX 750 Ti GPU.