This paper introduces an ultra-low-power amplifier-less front-end architecture for amperometric electrochemical sensing. The proposed architecture can simultaneously regulate the potential difference between the required electrodes and perform current readout for an electrochemical sensor. A dual-side potentiostat regulation loop comprising dynamic latched comparators in conjunction with digital loop filters and current-steering DACs is proposed, with its detailed operation discussed in this paper. Implemented in a standard 180 nm CMOS process, this design achieves a current measurement range of 114.3 dB. It can operate over a wide range of sampling frequencies FS (100 Hz ~ 100 MHz) and supply voltages (1 V ~ 1.8 V). The whole interface IC consumes only 3.50 nA current at 1.2 V supply at a clock frequency of 1-kHz.

This paper presents a multiphase clock and data recovery (CDR) circuit for high-speed (1.2-3.4 Gb/s) display driver ICs (DDIs) with a novel glitch-free bang-bang phase detector (BBPD). Compared to conventional BBPDs, which often suffer from sampling glitches caused by latch-delay mismatches and asynchronous data-edge interferences, the proposed BBPD employs a robust sampling network ensuring mutually exclusive data-edge valid events, thereby filtering invalid transitions and minimizing timing-induced jitter. An extensive comparison with conventional BBPDs highlights these improvements and clarifies how the proposed BBPD enhances phase detection integrity and overall stability in high-speed CDRs. Fabricated in a 0.18-μm CMOS process and integrated in a chip-on-film (COF) package along with other DDI's components, the proposed CDR demonstrates a clean output phase trajectory and an improved 97 ps output jitter (0.388 UI at 4 Gb/s) with only 20.1 mW power consumption including the equalizer power. The overall CDR performance is also validated through a comprehensive characterization using a shmoo plot across 1.4 V - 2.2 V supply voltages.

A hybrid high-voltage regulating charge pump is proposed for point-of-care electrokinetic concentration chip applications. The hybrid charge pump is composed of three cascaded sub-pumps. High efficiency, minimized area, wide output current range, and high regulated output voltage are achieved by selecting charge pump architectures that provide high voltage conversion gain with less number of stages. The proposed charge pump is designed and fabricated in 180 nm BCD process. Simulation results show that the proposed system provides a maximum efficiency of 48.26%, while providing a maximum output voltage of 65 V.

This paper presents a high-throughput impedance readout IC with a novel synchronous cyclic integration technique using a scalable capacitive transimpedance stage. The proposed technique removes the need for the low pass filter (LPF) in the readout chain and performs the I/Q demodulation within a single cycle. Fabricated in a 180-nm CMOS process, the proposed IC consumes 50 μW from a 1.2-V supply. It can measure impedances over a frequency of 100 Hz to 100 kHz with an accuracy of 99.7% and can achieve a throughput of 50 kSps at 100 kHz input frequency.

In this paper, a fully-integrated digital low dropout (DLDO) regulator is proposed utilizing a multi-bits shift handler (MBSH), decremental-gain PMOS array, and adaptive coarse loop controller to achieve fast load transient responses with improved line and load regulations. An undershoot-limiter loop (ULL) is also proposed to help to reduce the voltage undershoot peak during load current transients. To significantly mitigate the steady-state voltage ripples (VRIPP) and quiescent current (IQ), we propose a synchronized fine-loop freezer (FLF) in the fine loop of the DLDO that is only activated when VREGgets equal to VREF. The proposed DLDO was designed and fabricated in a 180-nm CMOS process with an active area of 0.22 mm2. The simulation results demonstrate that the proposed DLDO achieves ≤ 130 μV of VRIPPwhile maintaining a minimum dropout voltage of 20 mV and a peak current efficiency of 99.96 %.

This paper presents a novel high-throughput impedance measurement integrated circuit (IC) with baseline cancellation for neural EIT applications. The proposed technique uses a peak detector to obtain impedance magnitude every cycle. After taking the peak, the peak detector is reset to a DC baseline voltage. And, the signal swinging between the amplitude and the reset baseline is further amplified, allowing to measure small impedance variations even with a large baseline. The proposed IC fabricated in a 180-nm standard CMOS process can measure impedance variations of >0.1% baseline can be measured, while achieving high throughput of 100 kS/s at 100 kHz input frequency. Scalable design allows the proposed IC to support a wide frequency range from 100 Hz to 100 kHz with a power consumption from 31 μW to 39 μW from a 1.2-V supply.

This paper presents a digital low dropout (DLDO) regulator, which has very small steady-state voltage ripples (VRIPP) ofRIPP, a steady-state control based on a voltage-to-interval converter and a charge pump is proposed. To achieve a fast transient response, a dual-edge-triggered shift registers (DTSR) is used in the coarse loop. In addition, an analog-assisted (AA) loop is proposed to significantly mitigate the voltage undershoot in response to a load current (ILOAD) step. The DLDO was designed and fabricated in a 180-nm CMOS process with an active area of 0.253 mm2. The simulated results demonstrate that the proposed DLDO achieves a line regulation of 8 mV/V and a load regulation of 0.081 mV/mA while driving a maximum ILOADof 75 mA with a peak current efficiency of 99.93 %.