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Jiali Luan

dblp:234/6100 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2020
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 56% Integrated circuit design · 44%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
design for manufacturability
0.412020
Prediction of Multidimensional Spatial Variation Data via Bayesian Tensor Completion · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Integrated circuit design › process-voltage-temperature variation
process variation characterization
0.412020
Prediction of Multidimensional Spatial Variation Data via Bayesian Tensor Completion · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Electronic design automation › hardware verification and test
VLSI testing
0.112020
Prediction of Multidimensional Spatial Variation Data via Bayesian Tensor Completion · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020

Methods — techniques the papers use, named apart from their topics

variational bayesian inference · 0.4bayesian tensor completion · 0.4
YearPublicationVenuePosition
2020 Prediction of Multidimensional Spatial Variation Data via Bayesian Tensor Completion
abstract
This paper presents a multidimensional computational method to predict the spatial variation data inside and across multiple dies of a wafer. This technique is based on tensor computation. A tensor is a high-dimensional generalization of a matrix or a vector. By exploiting the hidden low-rank property of a high-dimensional data array, the large amount of unknown variation testing data may be predicted from a few random measurement samples. The tensor rank, which decides the complexity of a tensor representation, is decided by an available variational Bayesian approach. Our approach is validated by a practical chip testing data set, and it can be easily generalized to characterize the process variations of multiple wafers. Our approach is more efficient than the previous virtual probe techniques in terms of memory and computational cost when handling high-dimensional chip testing data.
Jiali Luan, Zheng Zhang 0005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1