Quantum Key Distribution (QKD) is increasingly adopted in security-critical links and future scenarios will include also space applications where radiation-induced faults can compromise the correctness and availability of the protocol. This risk is amplified on SRAM-based FPGAs, where configuration upsets can alter circuit behavior. Through this paper, we present a robust, heterogeneous FPGA/SoC platform to validate the reliability of QKD sifting on commercial off-the-shelf hardware. A lightweight RISC-V processor supervise the entire procedure, while the sifting accelerator is coupled with a lightweight monitoring unit to detects faults and triggers error correction through partial reconfiguration. The platform has been implemented on AMD ZCU102 UltraScale+ development boards and evaluated through fault injections. The adopted mitigation techniques allows downtime reduction by about 12000 × and lowers the sifting-module error rate by around 2%.

Reliable anomaly detection in satellite telemetry is critical for mission success, yet traditional threshold-based methods struggle with complex and evolving patterns.This work presents machine learning (ML) techniques to analyze high-dimensional telemetry data.Evaluations of real-world satellite telemetry datasets demonstrate the potential of ML to enhance spacecraft health monitoring and reduce manual intervention.

In recent years, Reconfigurable SoCs have emerged as a high-performance solution for embedded systems, addressing the increasing complexity of neural networks, balancing performance, cost, and adaptability. Flexible hardware accelerators, such as AMD’s Deep Learning Processing Units (DPUs), enable efficient computation across various domains, including safety-critical applications. However, soft errors remain a significant reliability concern, especially in harsh environments like space, where radiationinduced corruption of configuration memory poses a significant threat to FPGA-based systems. Most research on the reliability and robustness of deep learning models against soft errors has focused on application-level analyses, with comparatively little attention paid to architectural hardware faults. This paper introduces a resilience evaluation framework targeting AMD’s state-of-the-art DPU, comparing traditional application-level fault injection with hardware-aware fault injection performed on an actual hardware platform, a Kria KV260. Applying this methodology, we evaluated fourteen different deep neural network architectures and demonstrated that hardware-aware fault injections reveal critical vulnerabilities that applicationonly approaches fail to detect. Moreover, we investigated the source of different faults at the hardware level, enabling the identification of architectural resources that are more susceptible to errors. These insights are valuable to support the development of more robust deployment strategies and mitigation techniques tailored to FPGA-based deep learning accelerators.

Network Interface Cards (NICs) greatly evolved from simple basic devices moving traffic in and out of the network to complex heterogeneous systems offloading host CPUs from performing complex tasks on in-transit packets. These latter comprise different types of devices, ranging from NICs accelerating fixed specific functions (e.g., on-the-fly data compression/decompression, checksum computation, data encryption, etc.) to complex Systems-on-Chip (SoC) equipped with both general purpose processors and specialized engines (Smart-NICs). Similarly, Field Programmable Gate Arrays (FPGAs) moved from pure reprogrammable devices to modern heterogeneous systems comprising general-purpose processors, real-time cores and even AI-oriented engines. Furthermore, the availability of high-speed network interfaces (e.g., SFPs) makes modern FPGAs a good choice for implementing Smart-NICs. In this work, we extended the functionalities offered by an open-source NIC implementation (Corundum) by enabling time-aware traffic management in hardware, and using this feature to control the bandwidth associated with different traffic classes. By exposing dedicated control registers on the AXI bus, the driver of the NIC can easily configure the transmission bandwidth of different prioritized queues. Basically, each control register is associated with a specific transmission queue (Corundum can expose up to thousands of transmission and receiving queues), and sets up the fraction of time in a transmission window which the queue is supposed to get access the output port and transmit the packets. Queues are then prioritized and associated to different traffic classes through the Linux QDISC mechanism. Experimental evaluation demonstrates that the approach allows to properly manage the bandwidth reserved to the different transmission flows.

The rapid increase in the complexity of Field-Programmable Gate Arrays (FPGAs) is significantly impacting the efficiency of the design implementation flow. In particular, the routing process presents challenges in achieving computational efficiency and reducing time-to-solution due to the increasing on-chip resources and device complexity. This work introduces a novel router that leverages optimized data structures and memory access patterns to minimize memory consumption. Experimental results prove how the proposed approach can significantly reduce time-to-solution, identifying memory consumption as a barrier to achieving scalability and proposing solutions based on FPGA modular architecture to face it, achieving an average memory usage reduction of about 90 % and an average decrease of routing time of 40 %.

Field Programmable Gate Arrays (FPGAs) are gaining popularity in different fields, including space applications, where high computational capabilities are required; for this reason, FPGAs are often used as nodes in clusters. When considering mission-critical systems, reliability must be ensured, even in radiation environments such as space. Thus, it is necessary to define a way of monitoring the entire system, ensuring the correct behavior of each node. This work introduces the Beacon Controller, a module to be implemented on the FPGA elements of a cluster for real-time monitoring of the computational elements of the node.

Due to their high performance and flexibility, FPGAs have become an attractive solution for space applications. However, SRAM-based FPGAs are particularly sensitive to radiation-induced Single Event Effects that may lead to configuration memory corruption. We propose a methodology for enhancing the reliability of redundant design implemented on FPGAs. Statically analyzing the implementation of the circuit to identify and reduce the single points of failure of redundant systems, we can increase the system's robustness by controlling the placement phase.

The distributed embedded systems paradigm is a promising platform for high-performance embedded applications. We present a distributed algorithm and system based on cost-effective devices. The proof of concept shows how a parallelized approach leveraging a distributed embedded platform can address the computational of the Machine Learning K-Nearest Neighbors (K-NN) algorithm with large and heterogeneous datasets.

RISC-V soft processors are attractive for various applications, including mission-critical ones, thanks to their reduced costs and high flexibility. Despite their growing popularity, reliability analysis of such platforms is still in an early stage, mainly relying on system-level analysis only, leaving module-level assessment unexplored. Such limitations hinder the development of mitigation strategies that could effectively focus on vulnerabilities within a RISC-V soft processor system. We propose a methodology for evaluating the module-wise reliability of a RISC-V soft processor based on fine-grained fault injection, custom layout placement, and fault analysis. Through this approach, we can provide insights into the critical elements of the processor, identifying the most susceptible to faults, both at the module and system levels. The presented results enhance comprehension of weak points within the processor, paving the way for creating robust and dependable RISC-V systems.

Deep neural networks (DNNs) are increasingly used in critical applications from healthcare to autonomous driving. However, their predictions were shown to degrade in the presence of transient hardware faults, leading to potentially catastrophic and unpredictable errors. Consequently, several techniques have been proposed to increase the fault tolerance of DNNs by modifying network structures and/or training procedures, thereby reducing the need for costly hardware redundancy. There are, however, design or training choices whose impact on fault propagation has been overlooked in the literature. In particular, self-supervised learning (SSL), as a pretraining technique, was shown to improve the robustness of the learned features, resulting in better performance in downstream tasks. This study investigates the fault tolerance of several SSL techniques on image classification benchmarks, including several related to Earth Observation. Experimental results suggests that SSL pretraining, alone or in combination with fault mitigation techniques, generally improves DNNs' fault tolerance, although the performance gap vary among datasets and SSL techniques.

FPGAs have become a well-established solution for systems aiming for high performance and flexibility. FPGA-based SoCs have facilitated the integration of software programmability and custom hardware acceleration. The sensitivity to disturbance, the scarcity of CAD tools dedicated to evaluating robustness, and the drastic increase in on-chip components pose challenges to analyzing and assessing the reliability of reconfigurable systems in safety-critical domains. The current work proposes methodologies for accurate and efficient robustness analysis of Reconfigurable SoCs. It focuses on the heterogeneous components and modules embedded in Reconfigurable SoCs, such as soft and hard processors, host-device interfacing systems, and custom hardware accelerators. The research explores and provides the methodology and practical tools for developing and evaluating reliable applications on Reconfigurable SoCs, enabling detailed analyses of systems and their components.

Convolutional Neural Networks (CNNs) are quickly becoming one of the most common applications running on hardware accelerators. Considering Field Programmable Gate Arrays (FPGAs), due to their high flexibility and computational performance, they are suitable for fast classification tasks and therefore, pave the way for new machine learning inference approaches. In this work, we first designed a fully interconnected CNN architecture implementable on a single FPGA. Secondly, we developed a new Neural Node-oriented placement algorithm to enable resilient CNN accelerators on space-grade FPGAs. The proposed solution reduces the single event transient error sensitivity of CNN single neuron cores while achieving high performance and effective overall convolutional architecture fault tolerance. The developed approach has been applied and integrated into a state-of-the-art Radiation Tolerant FPGAs (RTG4) implementation flow. The experimental evaluation has been performed on a Microchip test board through benchmark application performance evaluation and transient error analysis. Experimental results demonstrate an improvement of 27.2% of the maximal working frequency and a reduction of the transient error sensitivity of about three times with respect to the previous mitigation approaches.

Field-Programmable Gate Arrays (FPGAs) are becoming increasingly important for space applications due to their high flexibility, performance, and complexity. In particular, soft-core processors like Xilinx Microblaze are commonly implemented using the programmable logic of FPGAs, making them suitable for embedded applications. However, the netlist of soft microprocessors can be corrupted by the effects of radiation-induced soft errors, in particular Single-Event Effects (SEUs) [1--5]. This work presents a detailed evaluation of the impact of radiation-induced architectural faults affecting the application benchmarks running on the FreeRTOS of the Microblaze embedded soft processor. The effect of Multiple Bits Upsets (MBU) faults during the execution of different software applications on FreeRTOS supported by Microblaze implemented on Zynq-7020 FPGA was evaluated, and the outcome of the software application was investigated. Please, notice that the developed platform is targeting only hardware faults and their impact on the execution of the software running in the operating system.

As GPGPUs gain popularity in HPC applications, there is a growing need to investigate their reliability for performance improvement and reduced computation overhead. In this paper, the authors propose a novel fault injection environment for NVIDIA GPGPU devices that can automatically inject faults into instructions at the SASS level by instrumenting the CUDA binary executable file. It can categorize faults into Silent Data Corruption, Detected Unrecoverable Error, and Hang, making it an effective tool for targeting the reliability evaluation of specific threads.

This paper describes an architecture-modulable FPGA framework comprising synthesis, mapping, place and route, and bitstream analysis and mitigation for circuits mapped on FPGAs suitable for aerospace applications. The framework has several benefits, including analysis of soft-error effects and comparison between different vendors and parts, compatibility with commercial and radiation-hardened FPGA, and the ability to individuate single point of failure and embeds different mitigation strategies such as Triple Modular Redundancy (TMR) and Single Event Transient (SET) filtering at the synthesis or the place and route level. In this work, we provide the description of the framework and the radiation-effects analysis and mitigation on a set of benchmark circuits implemented using the most recent FPGA devices families for aerospace such as AMD Xilinx Ultrascale, NanoXplore NG-Medium, Microchip Radiation-Tolerant ProASIC3, and Radiation-Tolerant G4. Finally, we present a comparative analysis of a benchmark circuit's performance and radiation sensitivity mapped on the different FPGA device manufacturers.

Assessing the reliability of modern devices running CNN algorithms is a very difficult task. Actually, the complexity of the state-of-the-art devices makes exhaustive Fault Injection (FI) campaigns impractical and typically out of the computational capabilities. A possible solution consists of resorting to statistical FI campaigns that allow a reduction in the number of needed experiments by injecting only a carefully selected small part of it. Under specific hypothesis, statistical FIs guarantee an accurate picture of the problem, albeit selecting a reduced sample size. The main problems today are related to the choice of the sample size, the location of the faults, and the correct understanding of the statistical assumptions. The intent of this paper is twofold: first, we describe how to correctly specify statistical FIs for Convolutional Neural Networks; second, we propose a data analysis on the CNN parameters that drastically reduces the number of FIs needed to achieve statistically significant results without compromising the validity of the proposed method. The methodology is experimentally validated on two CNNs, ResNet-20 and MobileNetV2, and the results show that a statistical FI campaign on about 1.21% and 0.55% of the possible faults, provides very precise information of the CNN reliability. The statistical results have been confirmed by the exhaustive FI campaigns on the same cases of study.

FPGAs' and programmable hardware's high performance and flexibility have made them a reasonable choice for space-oriented applications, although susceptible to soft errors. This paper proposes a comprehensive analysis of the effects of microarchitectural faults on soft processors due to radiations, identifying the hardware sources of errors and how they propagate to software-level.

The COVID-19 pandemic triggered a concerning rise in violence against women and children, known as The Shadow Pandemic. To address this, a Canadian foundation introduced the “Signal for Help” gesture to discreetly alert others in danger. However, the effectiveness of this approach depends on individuals recognizing and responding to the signal. In this paper, we propose an innovative solution that adopts the technology available in smart cities to detect the “Signal for Help” in real-time through surveillance footage. We developed and implemented a recognition algorithm on an affordable device that achieves accurate detection of the signal in 94 % of cases. This approach has the potential to improve the response to instances of violence, providing a reliable means of alerting authorities and support networks.

Last decade, the RISC-V soft processor has become popular due to the benefits such as transparency and availability of hardware implementations on reconfigurable devices such as SRAM-based FPGAs. However, these devices are highly sensitive to high-energy particles. In this work, we propose an implementation methodology that ranges from the hardening method applied at the Register Transfer Level (RTL) to the optimization of layout techniques acting on the place & route of the design. As a case study, the TMR-hardened Arithmetic Logic Unit (ALU) of the RISC-V soft processor implementation was taken and its reliability under different design layouts has been analyzed using fault injection campaigns. Experimental results show that the design reliability can be improved by applying ad hoc layout customization..

This paper encompasses three contributions by industry professionals and university researchers. The contributions describe different trends in automotive products, including both manufacturing test and run-time reliability strategies. The subjects considered in this session deal with critical factors, from optimizing the final test before shipment to market to in-field reliability during operative life.

As the adoption of SRAM-based FPGAs and Reconfigurable SoCs for High-Performance Computing increased in the last years, the use of Direct Memory Access for data transfer becomes a key feature of many reconfigurable applications even in the space industry. For such kinds of applications, radiation-induced effects are a serious issue that mines the correctness and success of mission-critical tasks. In this paper, we evaluate the effects of proton-induced errors on a DMA-based application implemented on a Xilinx Zynq-7020 FPGA in order to quantify the robustness of this module in a typical hardware-accelerated configuration. The obtained results confirm the high criticality of the DMA module on programmable logic. Moreover, the Multiple Bits Upsets effect has been evaluated. The most recurring patterns have been reported in order to provide further tools to better characterize the behavior of these systems under future fault injection campaigns, as demonstrated in the experimental results.

Multiprocessor system-on-chip such as embedded GPUs are becoming very popular in safety-critical applications, such as autonomous and semi-autonomous vehicles. However, these devices can suffer from the effects of soft-errors, such as those produced by radiation effects. These effects are able to generate unpredictable misbehaviors. Fault tolerance oriented to multi-threaded software introduces severe performance degradations due to the redundancy, voting and correction threads operations. In this paper, we propose a new fault injection environment for NVIDIA GPGPU devices and a fault tolerance approach based on error detection and correction threads executed during data transfer operations on embedded GPUs. The fault injection environment is capable of automatically injecting faults into the instructions at SASS level by instrumenting the CUDA binary executable file. The mitigation approach is based on concurrent error detection threads running simultaneously with the memory stream device to host data transfer operations. With several benchmark applications, we evaluate the impact of soft- errors classifying Silent Data Corruption, Detection, Unrecoverable Error and Hang. Finally, the proposed mitigation approach has been validated by soft-error fault injection campaigns on an NVIDIA Pascal Architecture GPU controlled by Quad-Core A57 ARM processor (JETSON TX2) demonstrating an advantage of more than 37% with respect to state of the art solution.

Three-dimensional Integrated Circuits (3-D ICs) have gained much attention as a promising approach to increase IC performance due to their several advantages in terms of integration density, power dissipation, and achievable clock frequencies. However, achieving a 3-D ICs resilient to soft errors resulting from radiation effects is a challenging problem. Traditional Radiation-Hardened-by-Design (RHBD) techniques are costly in terms of area, power, and performance overheads. In this work, we propose a new 3-D LUT design integrating error detection capabilities. The LUT has been designed on a two tiers IC model improving radiation resiliency by selective upsizing of sensitive transistors. Besides, an in-silicon radiation sensor adopting inverters chain has been implemented within the free volume of the 3-D structure. The proposed design shows a 37% reduction in sensitivity to SETs and an effective error detection rate of 83% without introducing any area overhead.

Reconfigurable SoCs are widely adopted in mission-critical tasks in aerospace and automotive. Though, one of their main drawbacks is the susceptibility to high-energy particles both in space and at sea level. Isolation Design Flow is a promising implementation approach to improve the reliability of circuits. However, considering the high number of modules in a complex circuit, especially when redundant techniques are applied, IDF requires a complex floorplanning stage. In this paper, the benefits of using IDF are evaluated, both for plain and hardened-by-redundancy designs. We propose an implementation methodology to tackle the complexity of applying IDF to TMR-based circuits that usually make the implementation approach unfeasible. The impact of different design policies on the reliability of the system is evaluated through fault injection campaigns. The proposed method is applied to the TMR-hardened CORDIC core implemented on Zynq AP-SoC and compared with other possible solutions. The results report a significant improvement in the TMR effectiveness when the proposed domains-based IDF is applied.

Static RAM modules are widely adopted in high performance systems. Single Event Effects (SEEs) resilient memories are required in many embedded systems applied in automotive and aerospace applications to increase their overall resiliency against SEEs. The current SEE resilient SRAM modules are obtained by applying radiation-hardened by design solutions which leads to elevated area overhead and difficulty to tune the resiliency capability with respect to the particle's radiation profile. To overcome these limitations, we propose a methodology for the analysis and mitigation of embedded SRAMs generated by the OpenRAM memory compiler. A technology-oriented radiation analysis tool is presented to support the interaction of the charged radiation particles with the SRAM layout and depict the sensitive transistors of the SRAM memory. A selective duplication of the sensitive transistors has been applied to the 6T-SRAM cell designed at the layout level. The designed cell is included in the OpenRAM compiler and used to generate a mitigated 8Kb SRAM-bank. We evaluated the SEEs sensitivity by comparative simulation-based radiation analysis observing a reduction more than 6 times with respect to the original 6T-SRAM cell for the SEE sensitivity at high energy heavy ions particles, with negligible degradation of operations margins and power consumption and area overhead of less than $\sim$ 4%.

Single event transients (SETs) have become increasingly problematic for modern CMOS circuits due to the continuous scaling of feature sizes and higher operating frequencies. Especially when involving safety-critical or radiation-exposed applications, the circuits must be designed using hardening techniques. In this brief, we present a new radiation-hardened-by-design full-adder cell on 45-nm technology. The proposed design is hardened against transient errors by selective duplication of sensitive transistors based on a comprehensive radiation-sensitivity analysis. Experimental results show a 62% reduction in the SET sensitivity of the proposed design with respect to the unhardened one. Moreover, the proposed hardening technique leads to improvement in performance and power overhead and zero area overhead with respect to the state-of-the-art techniques applied to the unhardened full-adder cell.

Nowadays, radiation-induced Single Event Transients are a leading cause of critical errors in CMOS nanometric integrated circuits. In this work, we propose a workflow for analyzing and mitigating nanometric CMOS integrated circuits to radiation-induced transient errors. The analysis phase starts with the developed Rad-Ray tool for mimicking the passage of the radiation particles through the silicon matter of the cells to identify the features of the generated transient pulses. The tool is integrated with an electrical simulator to evaluate the dynamic behavior of the transient pulses inserted and propagated in the circuit. A tunable mitigation solution is proposed by inserting the filtering block before the storage element, tuned based on the duration and amplitude of the expected transient pulse, identified in the analysis phase. Experimental results are achieved by applying the proposed approach on the 45 nm Flip-Flop component available in the FreePDK design kit, comparing the Dynamic Error Rate for the original Flip-Flop and the mitigated one which shows a reduction of sensitivity up to 56% with respect of the original version, with negligible degradation of performances.

Nowadays, increasing demand for High-Performance Systems produces significant growth in usage of Field Programmable Gate Arrays (FPGAs) for different applications thanks to their flexibility and high level of parallelism. Such systems rely on complex multi-layer Printed Circuit Board Assemblies (PCBA)with a few dozens of hidden layers, stacked microvias and high-density interconnects. Along with creating new test challenges, the increasing PCBA complexity elevates the criticality of defects in various subsystems. One of such sub-systems is a Power-Delivery-Network (PDN) with operating margin progressively reduced due to increasingly strict requirements of High-Performance applications. As a consequence, Marginal Defects and process variations in a PDN may create latent problems that will manifest in a particular condition thus compromising the overall system performance and causing malfunctions. In this paper we propose a new FPGA-based non-intrusive method to detect Marginal Defects in a PCBA PDN. The method is based on a monitoring circuit that measures signal delays caused by PDN variations and thus detects relevant anomalies. Additional ad-hoc PDN stress circuits have been developed to validate the measurement technique. Experimental results demonstrating the consistency of the proposed approach are obtained by comparing stress and non-stress scenarios.

SRAM-based FPGAs are widely used in mission critical applications. Due to the increasing working frequency and technology scaling of ultra-nanometer technology, Single Event Transients (SETs) are becoming a major source of errors for these devices. In this paper, we propose an approach for evaluating the Propagation-induced Pulse Broadening (PIPB) effect introduced by the logic resources traversed by transient pulses. The proposed methodology is applicable to any recent technology to provide SET analysis, necessary for an efficient mitigation technology. Experimental results achieved from a set of benchmarks are compared with fault injection experiments executed on a 28 nm SRAM-based FPGA to demonstrate the effectiveness of our technique.

In the last decades, FPGAs have been increasingly used in many different mission critical applications, such as the avionics and aerospace ones. Thus, research interest in studying faults in FPGAs has seen a sharp increase, especially for those applications that require high dependability and must operate in harsh environments. The increase of resources available in FPGA devices has caused a huge growth in routing complexity. Nowadays, more than 80% of transistors in modern FPGAs are related to the routing infrastructure. The analysis of faults related to routing structure of FPGA devices is a hard task due to the lack of tools working at low-level, limited information availability about interconnection structure from vendors and, above all, no automated testing workflow for such kind of resources. In this paper, we introduce PyXEL, an integrated environment realized to automatize the analysis of fault effects in FPGAs routing structure. PyXEL is a Python-based framework that allows to easily manipulate FPGAs bitstreams in order to inject specific faults and to analyze their behavior. Moreover, PyXEL provides an easy way to build and run experimental workflow interacting directly with Xilinx Vivado and ISE allowing to select routing resources to test and logically analyze results. We demonstrated the feasibility and the advantages of our approach exploiting PyXEL to gain insight into the electrical effects of faults in the routing interconnections of the Xilinx Artix-7.