Stochastic computing, an unconventional computing paradigm, often struggles with the costly random number generator (RNG)-based decorrelators. To solve this issue, we propose CoMix-D, a real-time solution that needs no RNGs. It uses a deterministic mixing architecture built from LiteSync, LiteDesync, and BitAggregator. Compared to state-of-the-art methods, CoMix-D achieves substantial savings of 80.1% in area and 59.9% in power without compromising accuracy.

As a vital security primitive, the true random number generator (TRNG) is a mandatory component to build trust roots for any encryption system. However, existing TRNGs suffer from bottlenecks of low throughput and high area-energy consumption. Additionally, the EDA design of TRNG for specific applications remains an unexplored area. To address these issues, in this work, we propose compact and high-throughput TRNGs based on dynamic hybrid, reinforcement strategies, and automated exploration. First, we present a dynamic hybrid entropy unit and reinforcement strategies to provide sufficient randomness. On this basis, we propose a high-efficiency dynamic hybrid TRNG (DH-TRNG) architecture. It exhibits portability to distinct process FPGAs and passes both NIST and AIS-31 tests without any post-processing. The experiments show it incurs only 8 slices with the highest throughput of 670Mbps and 620Mbps on Xilinx Virtex-6 and Artix-7, respectively. Compared to the state-of-the-art TRNGs, DH-TRNG has the highest Throughput/Slices∙ Power with 2.63× increase. In addition, we propose an automated exploration scheme as a preliminary EDA design for TRNG to better apply to resource-constrained scenarios. This scheme automatically explores TRNGs to meet the design requirements and further reduces the hardware overhead, indicating broad application prospects in TRNG automation design. Finally, we apply the proposed DH-TRNG and the results of automated exploration to stochastic computing for edge detection, achieving promising outcomes.

Stochastic computing (SC) generally suffers from long latency. One solution is to apply proper random number sources (RNSs) to generate the bit streams. However, existing RNS designs either have low accuracy or high hardware cost. To address this drawback, motivated by the fact that a uniform spatial distribution generally leads to high accuracy for an SC circuit, we propose a basic architecture to produce a uniform spatial distribution and a further detailed implementation of it. For the implementation, we further propose a method to optimize its hardware cost and an algorithm following a guiding principle to improve its accuracy. The method for hardware cost optimization allows hardware cost reduction while keeping the accuracy. Our experimental results show that the proposed implementation achieves both high accuracy and low hardware cost. For example, compared to a state-of-the-art stochastic number generator design, our design can reduce hardware cost by over 80%, while achieving higher accuracy

As a vital security primitive, the true random number generator (TRNG) is a mandatory component to build roots of trust for any encryption system. However, existing TRNGs suffer from bottlenecks of low throughput and high area-energy consumption. In this work, we propose DH-TRNG, a dynamic hybrid TRNG circuitry architecture with ultra-high throughput and area-energy efficiency. Our DH-TRNG exhibits portability to distinct process FPGAs and passes both NIST and AIS-31 tests without any post-processing. The experiments show it incurs only 8 slices with the highest throughput of 670Mbps and 620Mbps on Xilinx Virtex-6 and Artix-7, respectively. Compared to the state-of-the-art TRNGs, our proposed design has the highest Throughput/Slices Power with 2.63× increase.

Stochastic computing (SC) is an unconventional computing paradigm with unique features. Designing SC circuits is dramatically different from designing binary computing (BC) circuits. To support the agile design of SC circuits, we propose SCGen, a versatile generator framework, which provides users with a C++ interface to easily specify SC circuits and supports 1) accelerated accuracy simulation, 2) accelerated design space exploration (DSE) for accuracy maximization guided by simulated annealing (SA) and genetic algorithm (GA), 3) circuit optimization by random number source (RNS) sharing, 4) circuit verification via symbolic expression analysis, and 5) automatic Verilog code generation. Furthermore, we extend SCGen to also support agile design of hybrid SC-BC circuits. The experimental results show that our proposed DSE acceleration methods achieve up to 59x speedup, the DSE with SA and GA can get an average reduction of 4.0% and 12.7%, respectively, in accuracy loss compared to random search, and RNS sharing reduces the average area and power by 41% and 47%, respectively.

Stochastic computing (SC) is a promising computing paradigm for circuit design in the post-Moore era. It encodes data through stochastic bit streams (SBSs) and employs a randomizer to generate them, where the randomizer converts binary-encoded variables into stochastic formats and can optionally provide some SBSs of constant values. Owing to this, the randomizer generally plays a critical role in determining the accuracy of SC circuits and occupies a significant portion of their hardware cost. Therefore, it is crucial to apply proper randomizers to enhance the overall performance and efficiency of SC circuits. However, recent SC circuit designs often suffer from complex randomizers to ensure high accuracy. To address this issue, several efficient designs and optimization methods of randomizers have been proposed. In this paper, we review the common designs, the optimization methods, and the efficient application of randomizers, while discussing current challenges and future directions. By providing a brief overview, this survey underscores the critical role of randomizer design and optimization for efficient SC.

Univariate functions are widely used. Several recent works propose to implement them by an unconventional computing paradigm, stochastic computing (SC). However, existing SC designs either have a high hardware cost due to the area-consuming randomizer or a low accuracy. In this work, we propose a low-cost high-accuracy SC architecture for univariate functions. It consists of only a single stochastic number generator and a minimum number of D flip-flops. We also apply three methods, random number source (RNS) negating, RNS scrambling, and input scrambling, to improve the accuracy of the architecture. To efficiently configure the architecture to achieve a high accuracy, we further propose a design space exploration algorithm. The experimental results show that compared to the conventional architecture, the area of the proposed architecture is reduced by up to 76%, while its accuracy is close to or sometimes even higher than that of the conventional architecture.

Stochastic computing (SC) generally suffers from long latency. One solution is to apply proper random number sources (RNSs). Nevertheless, current RNS designs either have high hardware cost or low accuracy. To address the issue, motivated by that the uniform spatial distribution generally leads to a high accuracy for an SC circuit, we propose a basic architecture to generate the uniform spatial distribution and a further detailed implementation of it. For the implementation, we further propose a method to optimize its hardware cost and a method to optimize its accuracy. The method for hardware cost optimization can optimize the hardware cost without affecting the accuracy. The experimental results show that our proposed implementation can achieve both low hardware cost and high accuracy. Compared to the state-of-the-art stochastic number generator design, the proposed design can reduce 88% area with close accuracy.

One of the challenges stochastic computing (SC) faces is the high cost of stochastic number generators (SNG). A solution to it is inserting D flip-flops (DFFs) into the circuit. However, the accuracy of the stochastic circuits would be affected and it is crucial to capture it. In this work, we propose an efficient method to analyze the accuracy of stochastic circuits with DFFs inserted. Furthermore, given the importance of multiplication, we apply this method to analyze stochastic multiplier with DFFs inserted. Several interesting claims are obtained about the use of probability conversion circuits. For example, using weighted binary generator is more accurate than using comparator. The experimental results show the correctness of the proposed method and the claims. Furthermore, the proposed method is up to 560× faster than the simulation-based method.