Scan-based testing is a widely used design for testability method to ensure the ease of testing. In this method, the enhanced observability and controllability provided by the inserted scan chains significantly improve the ability to analyze circuit data. However, since the enhanced testability can be exploited by malicious users as a backdoor for attacks, countermeasures need to be implemented to prevent scan chain access by unauthorized users. Although much research on secure scan designs has been conducted, most proposed methods are vulnerable to architecture exposure by reverse engineering. Moreover, even the latest proposed methods are affected by issues related to untrustworthy test engineers. This study proposes a pattern-sequence-authentication-based secure scan that not only defends against reverse engineering-based attacks but also prevents test engineers from launching attacks using additional patterns other than the given pattern. The proposed method effectively addresses the issue of secret key leakage through valid test patterns by untrustworthy test engineers, which is a limitation of the existing methods. The experimental results show that the proposed method effectively defends against existing attack techniques and ensures high security performance.

Errors emerge as a major issue in the reliability of dynamic random access memory (DRAM). To enhance reliability, a two-tiered error correction code (ECC) architecture that comprises on-die ECC (OD-ECC) and system ECC (S-ECC) is adopted as a part of the standard for state-of-the-art high-bandwidth memory (HBM). However, conventional ECCs are insufficient to mitigate malfunctions of subwordline drivers (SWDs), a primary cause of errors. Moreover, the efficient co-design of two-tiered ECCs has not been sufficiently studied. To address these issues without increasing the size of check bits, this article proposes a two-tiered ECC architecture comprising an OD-ECC based on prediction and an S-ECC with data deinterleaving. The proposed OD-ECC predicts the SWD errors by leveraging the detection capabilities of two interleaved Reed-Solomon (RS) engines. In addition, the proposed S-ECC not only preserves strong error detection capability but also masks the misprediction effect of OD-ECC, where data deinterleaving renders additional errors caused by misprediction of OD-ECC to be bounded in the detectable range of the employed cyclic redundancy check (CRC). The experimental results demonstrate that the proposed two-tiered ECC can significantly enhance the error correction capability for SWD errors while maintaining the correction capability for other types of errors.

Scan chain diagnosis is an important step in solving yield problems in early manufacturing processes. The higher the diagnostic resolution, the better the yield in the initial process. In the conventional scan chain architecture, if failed scan chain data are observed during scan mode, all the shifted data through a stuck-at faulty cell are contaminated. As a result, only a single fault can be diagnosed, and there are difficulties in diagnosing multiple stuck-at fault locations. The number of multiple faults has increased significantly, increasing the cost of physical fault analysis. In addition, it is difficult to diagnose faults with a high resolution because there are many candidate faults early in the process. In this article, a new hardware architecture with data duplication is proposed to diagnose fault locations by deliberate voltage collision even if multiple faults occur. The resources required for the diagnosis include a minimum of one good scan chain, a diagnosis circuit, and a diagnostic line. Experimental results show that the proposed method has lower hardware and routing overhead and fewer additional pin counts than the existing method. The diagnostic speed is also faster, and the larger the number of scan chains (the larger the circuit), the higher the diagnostic performance, which has advantages over conventional methods.