Due to its dominance in the whole chip area, power and delay, the FPGA interconnect circuits are traditionally designed by full custom design method. We present an automated transistor-level sizing optimization methodology for GRM FPGA interconnect circuits. In order to get accurate and effective predicated area, the commonly used diffusion sharing, transistor folding and inputs sharing are considered. To get the accurate and effective delay value, we avoid the inaccuracy of using linear device model, and use two schemes to build wire model: the wire within a circuit and the wire between interconnect circuits. To decrease simulation time, we propose multi-thread acceleration method and the Minimum-Final-Delay (MFD) algorithm which optimizes interconnect circuit as a whole, not separated part. For switch box optimization, MFD algorithm requires 38% less number of simulations than COFFE's algorithm. We use 65nm CMOS process technology for evaluation. For different optimization strategy, we emphasize either representative critical path delay or overall layout area. Compare to full-custom design method, the global cost can be decrease by 3% ~ 17%. For different transistor sizing combinations, 10/50 threads can be ~ 9X/15X faster than single-thread. Compared with the manual design method, our optimization methodology explores larger design space, and it decreases the circuit design optimization time from months to hours.

Due to its dominance in FPGA area and delay, the interconnect circuit is traditionally designed and optimized in full customized fashion, which can be extremely time consuming. In this paper, we propose an automated transistor-level sizing optimization method for the widely-used General Routing Matrix FPGA interconnect circuits with the following three features: (1) an area model that takes into account the commonly used diffusion sharing, transistor folding and inputs sharing techniques in order to have an accurate area predication; (2) an accurate and effective non-linear delay model that treats the wire within a circuit and the wire between interconnect circuits separately; (3) a multi-thread acceleration method and the Minimum-Final-Delay algorithm to speed-up the simulation. The global optimization cost is measured by the product of the interconnect circuit area and the representative path delay based on our proposed models. The cost reduces 10.9%, when we use 65nm CMOS process chip for evaluation. The simulation time for different transistor sizing combinations is improved by 9X and 15X when 10 and 50 threads are used, respectively, faster than single-thread. Compared with the manual design method, our proposed optimization approach explores a larger design space and reduces the optimization time from months to hours.