Demo Data from VLDB 2026 / reviewers in the wild / expert
Chia-Wei Liang
dblp:236/8683
· DBLP profile ↗
2ranked-venue papers
0as first author
2since 2021 · last 2025
0000-0003-3109-1868ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 75% Hardware reliability and fault tolerance · 25% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
digital circuit design |
0.6 | 1 | 2022 | SEM-latch: a lost-cost and high-performance latch design for mitigating soft errors in nanoscale CMOS process · DAC 2022 |
Integrated circuit design › digital circuit design › sequential circuit design
latch design |
0.6 | 1 | 2022 | SEM-latch: a lost-cost and high-performance latch design for mitigating soft errors in nanoscale CMOS process · DAC 2022 |
Integrated circuit design › low-power circuit design
low-power latch design |
0.6 | 1 | 2022 | SEM-latch: a lost-cost and high-performance latch design for mitigating soft errors in nanoscale CMOS process · DAC 2022 |
Hardware reliability and fault tolerance › soft errors
soft error mitigation |
0.6 | 1 | 2022 | SEM-latch: a lost-cost and high-performance latch design for mitigating soft errors in nanoscale CMOS process · DAC 2022 |
Methods — techniques the papers use, named apart from their topics
reference voltage generator · 0.6QUATRO extension · 0.6
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Designing Radiation-Hardened D Flip-Flop with Reduced Latency and Area Using Filtering BufferabstractIn safety-critical applications such as biomedical and automotive electronics, soft errors induced by radiation particles pose a significant reliability concern. This paper presents a novel Filtering Buffer-based D Flip-Flop (FB-DFF) designed to enhance radiation hardening while minimizing area and timing overheads. The FB-DFF integrates a Filtering Buffer (FB) and an Auto Delay Element (ADE) to effectively filter out transient errors and ensure the correct input signal is latched. The Single-Master Dual-Slaves (SMDS) architecture further prevents error propagation to the output. Experimental results demonstrate that FB-DFF can resist radiation particles below 77 LET, providing full protection against both Single Event Transient (SET) and Single Event Upset (SEU). Compared to existing designs, FB-DFF reduces area overhead by 44% and timing overhead by 144% at the chip level, making it a highly efficient solution for radiation-hardened applications. The proposed FB-DFF offers a balanced trade-off between radiation hardening capability, area, and timing performance, making it suitable for integration into various safety-critical systems. Nelson M.-C. Wu, Lowry P.-T. Wang, Chia-Wei Liang, Charles H.-P. Wen, Herming Chiueh |
VTS | 3 |
| 2022 | SEM-latch: a lost-cost and high-performance latch design for mitigating soft errors in nanoscale CMOS processabstractSoft errors (primarily single-event transients (SET) and single-event upsets (SEU)) are receiving increased attention due to the increasing prevalence of automotive and biomedical electronics. In recent years, several latch designs have been developed for SEU/SET protection, but each has its own issues regarding timing, area, and power. Therefore, we propose a novel soft-error mitigating latch design, called SEM-Latch, which extends QUATRO and incorporates a speed path whereas embedding a reference voltage generator (RVG) for simultaneously improving timing, area, and power in 45nm CMOS process. SEM-Latch effectively reduces the power, area, and PDAP (product of delay, area, and power) by an average of 1.4%, 12.5%, and 8.7%, respectively, in comparison to a previous latch (HPST) with equivalent SEU protection. Furthermore, in comparison to AMSER-Latch, SEM-Latch reduces area, timing overhead and PDAP by 27.2%, 48.2%, and 60.2%, respectively, to provide 99.9999% particle rejection rate for SET protection. Zhong-Li Tang, Chia-Wei Liang, Ming-Hsien Hsiao, Charles H.-P. Wen |
DAC | 2 |