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Sotoju Asai

dblp:237/2643 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1984
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 87% Integrated circuit design · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
physical design		 0.011984
A Hierarchical Standard Cell Approach for Custom VLSI Design · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1984
Electronic design automation › physical design › cell layout
standard cell layout		 0.011984
A Hierarchical Standard Cell Approach for Custom VLSI Design · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1984
Integrated circuit design › VLSI design
custom VLSI design		 0.011984
A Hierarchical Standard Cell Approach for Custom VLSI Design · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1984

Methods — techniques the papers use, named apart from their topics

hierarchical design · 0.0CAD system · 0.0
YearPublicationVenuePosition
1984 A Hierarchical Standard Cell Approach for Custom VLSI Design
abstract
A custom VLSI design technique, using an integrated CAD system is described. The design system features on the hierarchical design process and layout design capability by system designers (customers). As for application, high-performance LSI's for 16-bit CPU were developed. The LSI design was accomplished in a short period (three months with three designers) due to the hierarchical standard cell approach. The LSI chip contains about 20 K transistors in an 8.84 mm X 8.88 mm die area. High-speed operation (machine cycle = 200 ns) and a high density of 291 transistors/mm2 were obtained with low power consumption (1.2 W) owing to the mixed-MOS type standard cell library and this approach.
Takeshi Tokuda, Jiro Korematsu, Osamu Tomisawa, Sotoju Asai, Isao Ohkura, Tatsuya Enomoto
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4