Memory access patterns have been leveraged to break cryptosystems and exfiltrate data from trusted execution environments (TEEs), among other exploits. This category of attacks, termed side channels, abuses a program’s data-dependent execution patterns to infer secret information. Several proposed techniques aim to obfuscate or eliminate data-dependent execution patterns or hinder attackers’ measurements in order to prevent side-channel attacks. Oblivious RAM (ORAM) has emerged as a successful mechanism for privatizing memory accesses in a provably secure manner. This cryptographic technique has been designed to both obfuscate server requests for cloud settings and to conceal memory accesses for TEEs. Existing ORAM schemes have primarily been characterized by their asymptotic complexity. Current analyses either fail to evaluate ORAM performance on real systems or lack detailed CPU metrics needed to identify bottlenecks and improve future implementations.In this paper, we provide the first workload characterization of ORAM for secure enclave applications. We analyze the performance of seven foundational ORAM schemes across ten benchmarks. Using a subset of six synthetic workloads, we study how execution time scales with increased working set size, and whether memory access patterns affect each ORAM’s performance. We then combine these workloads with four additional application benchmarks from VIP-Bench and perform a topdown microarchitectural analysis to identify critical bottlenecks. Our findings provide valuable insights that can guide developers in creating more efficient ORAM implementations and selecting schemes best suited to their applications.

Embedded systems are evolving in complexity, leading to the emergence of multiple threats. The co-design and execution of software on the embedded systems further exacerbate the attack surface, making them more vulnerable to sophisticated attacks. As embedded systems are used in critical areas, ensuring their security is crucial. In this special session paper, primarily four major topics regarding embedded systems’ security are discussed. Firstly, this paper initially explores timing channel analysis at a microarchitectural level in heterogeneous hardware to address the security challenges. It then delves into exploring software-based fuzzing techniques to detect vulnerabilities and enhance embedded system security. Additionally, the paper discusses strategies for improving security in IoT devices with a layered defense strategy known as Snowflake IoT. Finally, it examines approaches to securing large and complex monolithic systems. The challenges and opportunities for securing the embedded systems according to the scale and type of attacks.

Low-trust architectures work on, from the viewpoint of software, always-encrypted data, and significantly reduce the amount of hardware trust to a small software-free enclave component. In this paper, we perform a complete formal verification of a specific low-trust architecture, the Sequestered Encryption (SE) architecture, to show that the design is secure against direct data disclosures and digital side channels for all possible programs. We first define the security requirements of the ISA of SE low-trust architecture. Looking upwards, this ISA serves as an abstraction of the hardware for the software, and is used to show how any program comprising these instructions cannot leak information, including through digital side channels. Looking downwards this ISA is a specification for the hardware, and is used to define the proof obligations for any RTL implementation arising from the ISA-level security requirements. These cover both functional and digital side-channel leakage. Next, we show how these proof obligations can be successfully discharged using commercial formal verification tools. We demonstrate the efficacy of our RTL security verification technique for seven different correct and buggy implementations of the SE architecture.

Data-oblivious programs have gained popularity due to their application in security, but are often dismissed because of anticipated performance loss. In order to better understand these performance concerns, this paper details the first performance characterization of data-oblivious programs. We study mechanical data-oblivious transformations applied to twenty workloads from the VIP-Bench benchmark suite and find that, overall, performance overheads vary widely, with a geomean slowdown of 7.4×. This variance can be attributed to whether or not the data-oblivious transformations affect the workload’s asymptotic complexity. Performance overheads are much lower for the fourteen workloads whose complexity is unaffected, at 1.9× geomean. Further, by reducing control hazards, we find that dataoblivious transformations often result in improved per-instruction performance (e.g., better branch and memory performance) and increase the number of instructions the processor can execute in parallel (e.g., IPC). Leveraging lessons from analyzing these overheads, we study four notably slow data-oblivious workloads and show how algorithmic changes can significantly improve performance–achieving an average 86.4× speedup over the mechanically produced baseline programs. While data-oblivious program execution often incurs overheads, the contributions of this paper show that these overheads can be overcome by compiler and algorithmic optimizations, bringing us closer to achieving efficient and widely-used data-oblivious programs.

There is an increasing body of work in the area of hardware defenses for software-driven security attacks. A significant challenge in developing these defenses is that the space of security vulnerabilities and exploits is large and not fully understood. This results in specific point defenses that aim to patch particular vulnerabilities. While these defenses are valuable, they are often blindsided by fresh attacks that exploit new vulnerabilities. This article aims to address this issue by suggesting ways to make future defenses more durable based on an organization of security vulnerabilities as they arise throughout the program life cycle. We classify these vulnerability sources through programming, compilation, and hardware realization, and we show how each source introduces unintended states and transitions into the implementation. Further, we show how security exploits gain control by moving the implementation to an unintended state using knowledge of these sources and how defenses work to prevent these transitions. This framework of analyzing vulnerability sources, exploits, and defenses provides insights into developing durable defenses that could defend against broader categories of exploits. We present illustrative case studies of four important attack genealogies—showing how they fit into the presented framework and how the sophistication of the exploits and defenses have evolved over time, providing us insights for the future.

Attacks often succeed by abusing the gap between program and machine-level semantics-- for example, by locating a sensitive pointer, exploiting a bug to overwrite this sensitive data, and hijacking the victim program's execution. In this work, we take secure system design on the offensive by continuously obfuscating information that attackers need but normal programs do not use, such as representation of code and pointers or the exact location of code and data. Our secure hardware architecture, Morpheus, combines two powerful protections: ensembles of moving target defenses and churn. Ensembles of moving target defenses randomize key program values (e.g., relocating pointers and encrypting code and pointers) which forces attackers to extensively probe the system prior to an attack. To ensure attack probes fail, the architecture incorporates churn to transparently re-randomize program values underneath the running system. With frequent churn, systems quickly become impractically difficult to penetrate. We demonstrate Morpheus through a RISC-V-based prototype designed to stop control-flow attacks. Each moving target defense in Morpheus uses hardware support to individually offer more randomness at a lower cost than previous techniques. When ensembled with churn, Morpheus defenses offer strong protection against control-flow attacks, with our security testing and performance studies revealing: i) high-coverage protection for a broad array of control-flow attacks, including protections for advanced attacks and an attack disclosed after the design of Morpheus, and ii) negligible performance impacts (1%) with churn periods up to 50 ms, which our study estimates to be at least 5000x faster than the time necessary to possibly penetrate Morpheus.