Demo Data from VLDB 2026 / reviewers in the wild / expert
Shreyas Singh
dblp:238/5568
· DBLP profile ↗
6ranked-venue papers
1as first author
6since 2021 · last 2025
0009-0004-7338-0267ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Graphics, computer vision, multimedia, augmented reality and games · 3 · 1 first-author · 3 since 2021Artificial intelligence and machine learning · 2 · 1 first-author · 2 since 2021Systems, architecture and hardware · 2 · 2 since 2021Security and privacy · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Memory systems · 46% Processor architecture and microarchitecture · 23% Hardware accelerators and domain-specific architectures · 23% | |
| Computer graphics and multimedia
1 paper |
Computational photography and imaging · 100% | |
| Network and information security
1 paper |
Cryptographic primitives and cryptanalysis · 50% Cryptographic protocols and secure computation · 50% |
Topics — the 9 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Computational photography and imaging › computational optics
coded aperture imaging |
0.8 | 1 | 2024 | Passive Snapshot Coded Aperture Dual-Pixel RGB-D Imaging · CVPR 2024 |
Computational photography and imaging
depth sensing |
0.8 | 1 | 2024 | Passive Snapshot Coded Aperture Dual-Pixel RGB-D Imaging · CVPR 2024 |
Memory systems › cache › prefetching
data prefetching |
0.8 | 1 | 2024 | PATHFINDER: Practical Real-Time Learning for Data Prefetching · ASPLOS (3) 2024 |
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.8 | 1 | 2024 | Hyena: Balancing Packing, Reuse, and Rotations for Encrypted Inference · SP 2024 |
Memory systems
memory hierarchy |
0.8 | 1 | 2024 | PATHFINDER: Practical Real-Time Learning for Data Prefetching · ASPLOS (3) 2024 |
Processor architecture and microarchitecture
microarchitectural prediction |
0.8 | 1 | 2024 | PATHFINDER: Practical Real-Time Learning for Data Prefetching · ASPLOS (3) 2024 |
Cryptographic primitives and cryptanalysis
homomorphic encryption |
0.2 | 1 | 2024 | Hyena: Balancing Packing, Reuse, and Rotations for Encrypted Inference · SP 2024 |
Cryptographic protocols and secure computation
secure multiparty computation |
0.2 | 1 | 2024 | Hyena: Balancing Packing, Reuse, and Rotations for Encrypted Inference · SP 2024 |
Performance modeling and evaluation
workload characterization |
0.2 | 1 | 2024 | PATHFINDER: Practical Real-Time Learning for Data Prefetching · ASPLOS (3) 2024 |
Methods — techniques the papers use, named apart from their topics
pipelining · 1.5homomorphic encryption · 1.5stride detection · 0.8online learning · 0.8neural network · 0.8multiparty computation · 0.8multi-party computation · 0.8end-to-end optimization · 0.8dual-pixel sensing · 0.8coded aperture · 0.8address correlation · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Visual Prompting Through Image MinesabstractVisual prompting aims to enhance the performance of vision-language models (VLMs), which, despite their remarkable capabilities, often struggle with dense, detailed images, leading to incorrect answers or hallucinations. We propose Visual Prompting Through Image Mines , a novel algorithm that leverages attention patterns from a base VLM to generate image crops for improved visual grounding. Specifically, we extract attention values from output text tokens in the LLaVA-8B model, overlay them onto image patches to create an attention graph, and apply a modified breadth-first search (BFS) to identify key regions as image crops. Using the SigLIP model, we refine these regions into Image Mines, retaining only the most relevant crops. Our approach supports both single-image and multi-image inference setups, delivering superior performance. It consistently outperforms existing visual prompting methods in nearly all scenarios. Kalash Shah, J. Snehan, Gautam Bhutani, Kunal Singh, Shreyas Singh |
ICIP | 5 |
| 2024 | PATHFINDER: Practical Real-Time Learning for Data PrefetchingabstractData prefetching is vital in high-performance processors and a large body of research has introduced a number of different approaches for accurate prefetching: stride detection, address correlating prefetchers, delta pattern detection, irregular pattern detection, etc. Most recently, a few works have leveraged advances in machine learning and deep neural networks to design prefetchers. These neural-inspired prefetchers observe data access patterns and develop a trained model that can then make accurate predictions for future accesses. A significant impediment to the success of these prefetchers is their high implementation cost, for both inference and training. These models cannot be trained in real-time, i.e., they have to be trained beforehand with a large benchmark suite. This results in a large model (that increases the overhead for inference), and the model can only successfully predict patterns that are similar to patterns in the training set. James Patrick Mcmahon, Sumanth Gudaparthi, Shreyas Singh, Rajeev Balasubramonian |
ASPLOS (3) | 4 |
| 2024 | HDRSplat: Gaussian Splatting for High Dynmaic Range 3D Scene Reconstruction from Raw Images
Shreyas Singh, Aryan Garg, Kaushik Mitra |
BMVC | 1 |
| 2024 | Passive Snapshot Coded Aperture Dual-Pixel RGB-D ImagingabstractPassive, compact, single-shot 3D sensing is useful in many application areas such as microscopy, medical imaging, surgical navigation, and autonomous driving where form factor, time, and power constraints can exist. Ob-taining RGB-D scene information over a short imaging distance, in an ultra-compact form factor, and in a passive, snapshot manner is challenging. Dual-pixel (DP) sensors are a potential solution to achieve the same. DP sensors collect light rays from two different halves of the lens in two interleaved pixel arrays, thus capturing two slightly different views of the scene, like a stereo camera system. However, imaging with a DP sensor implies that the defocus blur size is directly proportional to the disparity seen between the views. This creates a tradeoff between disparity estimation vs. deblurring accuracy. To improve this tradeoff effect, we propose CADS (Coded Aperture Dual-Pixel Sensing), in which we use a coded aperture in the imaging lens along with a DP sensor. In our approach, we jointly learn an optimal coded pattern and the reconstruction algorithm in an end-to-end optimization setting. Our resulting CADS imaging system demonstrates improvement of> 1.5 dB PSNR in all-in-focus (AIF) estimates and 5-6% in depth estimation quality over naive DP sensing for a wide range of aperture settings. Furthermore, we build the proposed CADS prototypes for DSLR photography settings and in an endoscope and a dermoscope form factor. Our novel coded dual-pixel sensing approach demonstrates accurate RGB-D reconstruction results in simulations and real-world experiments in a passive, snapshot, and compact manner. Bhargav Ghanekar, Salman Siddique Khan, Pranav Sharma, Shreyas Singh, Vivek Boominathan, Kaushik Mitra, Ashok Veeraraghavan |
CVPR | 4 |
| 2024 | Hyena: Balancing Packing, Reuse, and Rotations for Encrypted InferenceabstractDeep neural networks are widely used in a range of commercial services. Many of these services are hosted on the cloud, requiring users to send their personal data to the cloud. This, in turn, exposes the user’s private and sensitive data to several third parties. To address this problem, Homomorphic Encryption (HE) has been introduced, where the user encrypts their data before sending it to the cloud; the cloud performs operations on encrypted data and returns a ciphertext that the user must then decrypt. While this approach keeps user data private, it demands orders of magnitude more computation and data movement. It is, therefore, imperative to design hardware/software techniques to lower the overheads when executing AI services under Homomorphic Encryption schemes.In this paper, we consider a range of HE implementations for AI inference and address the key bottlenecks in state-of-the-art frameworks. We start by making the case for a hybrid HE and Multi-Party Computation (MPC) scheme that is more practical than pure Fully HE. This paper introduces new techniques at various levels: (i) we introduce new data packing techniques that result in lower data movement, (ii) we introduce new dataflows that increase reuse and reduce other costly HE operations (rotations, key switching, NTT conversion), (iii) we evaluate Hyena on a balanced pipelined architecture that efficiently handles the above primitives. The resulting framework, Hyena (new packing + dataflow), achieves better performance and energy than several packing baselines. Compared to the widely used Channel-packing, Hyena is 38× faster and achieves 162× lower energy consumption, with an overall ResNet20 inference end-to-end latency of 11.4 ms, using a 163 mm2accelerator dissipating 16.75 W. Sarabjeet Singh, Shreyas Singh, Sumanth Gudaparthi, Xiong Fan, Rajeev Balasubramonian |
SP | 2 |
| 2021 | Zero Aware Configurable Data Encoding by Skipping Transfer for Error Resilient ApplicationsabstractData transfer across DRAM channels accounts for nearly a quarter of the total energy consumption of DDR4 DRAMs. Modern applications with high bandwidth requirements further increase channel energy consumption. However, channel energy consumption is dependent on data being transferred. Pseudo Open Drain (POD) asymmetric termination, used in current DDR4 systems, consumes energy only when 1's are being transmitted over the channels. Many modern applications, including AI/ML ones are resilient to errors in data, and can work well with approximate data. This resilience can vary widely across and within applications, which provides a number of ways for exploiting these characteristics to save data transfer energy across the DRAM channel. However, all DRAM data encoding schemes have been targeted towards applications that require exact data and are not approximation resilient. In this paper, we propose Zero Aware Configurable Data Encoding by Skipping Transfer (ZAC-DEST), a data encoding scheme to reduce the energy consumption of DRAM channels, specifically targeted towards approximate computing and error resilient applications. ZAC-DEST exploits the similarity between recent data transfers across channels and information about error resilience behaviour of applications to reduce on-die termination and switching energy by reducing the number of 1's transmitted over the channels. ZAC-DEST also provides a number of knobs for trading off application's accuracy for energy savings, and vice versa, and can be applied to both training and inference. We apply ZAC-DEST to five machine learning applications. On average, across all applications and configurations, we observed a reduction of 40% in termination energy and 37% in switching energy as compared to the state of the art data encoding technique BD-Coder with an average output quality loss of 10%. We show that if both training and testing are done assuming the presence of ZAC-DEST, the output quality of the applications can be improved upto 9× as compared to when ZAC-DEST is only applied during testing leading to energy savings during training and inference with increased output quality. Chandan Kumar Jha 0001, Shreyas Singh, Riddhi Thakker, Manu Awasthi, Joycee Mekie |
IEEE Trans. Circuits Syst. I Regul. Pap. | 2 |