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Kihyo Moon

dblp:239/0111 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2025
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 1 · 1 since 2021Systems, architecture and hardware · 1 · 1 since 2021Databases, data management, data science and information retrieval · 1 · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 61% Memory systems · 30% GPUs and heterogeneous computing · 9%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.912025
PAISE: PIM-Accelerated Inference Scheduling Engine for Transformer-based LLM · HPCA 2025
Memory systems
processing-in-memory
0.912025
PAISE: PIM-Accelerated Inference Scheduling Engine for Transformer-based LLM · HPCA 2025
Hardware accelerators and domain-specific architectures › machine learning accelerator › transformer accelerator
transformer inference accelerator
0.912025
PAISE: PIM-Accelerated Inference Scheduling Engine for Transformer-based LLM · HPCA 2025

Methods — techniques the papers use, named apart from their topics

transaction-wise interleave-batched GEMM · 0.9scheduling algorithm · 0.9data layout adjustment · 0.9
YearPublicationVenuePosition
2025 DSDE: Dynamic Speculative Decoding with KLD Stability for Real-World Serving
Kihyo Moon, Minsung Jang, Eunjoo Jeon
IEEE Big Data3
2025 PAISE: PIM-Accelerated Inference Scheduling Engine for Transformer-based LLM
abstract
Transformer-based Large Language Models (LLMs) demand significant computational and memory resources due to the autoregressive token generation in decoder blocks. In particular, the attention layer in LLM models has low arithmetic intensity but high memory traffic, thus requiring frequent updates to the KV matrices with each decoder iteration. As a result, LLM inference becomes memory bound, leading to increased latency. To address this, we introduce PAISE, a framework leveraging Processing-In-Memory (PIM) technology to offload memory-intensive tasks. PAISE employs GPU-PIM heterogeneous computing resources to optimize inference operations in transformer-based LLMs. The framework comprises (i) a scheduling algorithm that decides which operations to offload to PIM based on model configuration and PIM hardware specifications and (ii) an enhanced PIM kernel that performs transaction-wise interleave-batched GEMM (General Matrix Multiplication) operations, maximizing data throughput via data layout adjustments. We implemented PAISE on the GPT-2 and Llama2-7B models using an AMD MI100 GPU with HBM-PIM devices. Our evaluations show that offloading the attention layer to PIM reduces execution time by up to 48.3% compared to GPU-only inference, demonstrating PAISE’s significant potential to enhance the efficiency of LLM inference, which could lead to faster and more efficient AI applications.
Hyojung Lee, Daehyeon Baek, Jimyoung Son, Jieun Choi, Kihyo Moon, Minsung Jang
HPCA5