VLDB 2026 Research / reviewers in the wild / expert
Mengqi Liu 0001
dblp:239/5467 · also Meng-qi Liu 0001
· DBLP profile ↗
12ranked-venue papers
2as first author
9since 2021 · last 2025
0000-0001-7027-4566ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 6 · 6 since 2021Software engineering, systems software and programming languages · 4 · 2 first-author · 2 since 2021Security and privacy · 1 · 1 since 2021Theory of computation · 1Applied, interdisciplinary, general and emerging computing · 1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | New Evolution of Hoyan: Enhancing Scalability, Usability, and Accuracy for Alibaba's Global WAN VerificationabstractThe network verification system Hoyan has been deployed for Alibaba Cloud's wide-area network (WAN) for years and achieved considerable success in preventing misconfiguration-caused network incidents. However, recent years have seen the emergence of new challenges in scalability, usability, and accuracy for Hoyan. This paper presents the new evolution of Hoyan to address these challenges. First, to support the large increase in the number of routers and prefixes on our WAN, Hoyan's simulation has evolved from a centralized fashion to a distributed framework, which improves the efficiency by 5 times and can scale to O(104) routers, millions of prefixes, and billions of flows. Second, to improve Hoyan's usability in checking route change intents, we developed a specification language RCL, which supports the easy specification and automatic verification of route change intents. Third, to ensure high accuracy we enhanced Hoyan's accuracy diagnosis framework, which helped us identify and fix dozens of implementation and modeling issues. Hoyan is used on a daily basis for our WAN. It supports O(100) verification requests each week, prevents O(10) incidents each year, and helps reduce the percentage of misconfiguration-caused network incidents from 56% to 5%. Yifei Yuan 0001, Fangdan Ye, Jingkai Zhang, Mengqi Liu 0001, Yuyang Sang, Ruizhen Yang, Duncheng She, Zhiqing Ye, Tianchen Guo, Xinji Tang, Zhongyu Guan, Lingpeng Su, Ci Wang, Ruiyang Feng, Zhonghui Xie, Xianlong Zeng, Dennis Cai, Ennan Zhai |
SIGCOMM | 5 |
| 2024 | Sirius: Composing Network Function Chains into P4-Capable Edge Gateways
Jiamin Cao, Mengqi Liu 0001, Dennis Cai, Ennan Zhai |
NSDI | 4 |
| 2024 | A General and Efficient Approach to Verifying Traffic Load Properties under Arbitrary k FailuresabstractThis paper presents YU, the first verification system for checking traffic load properties under arbitrary failure scenarios that can scale to production Wide Area Networks (WANs). Building a practical YU requires us to address two challenges in terms of generality and efficiency. The state-of-the-art efforts either assume shortest-path-based forwarding (e.g., QARC) or only target single-failure reasoning (e.g., Jingubang). As a result, the former inherently cannot generalize to widely used protocols (e.g., SR and iBGP) that are beyond shortest-path forwarding, while the latter cannot efficiently handle arbitrary failure scenarios. For the generality challenge, we propose an approach inspired by symbolic execution, called symbolic traffic execution, to model the forwarding behavior of a range of practically deployed protocols (e.g., eBGP, iBGP, iGP, and SR) under failure scenarios. For the efficiency challenge, we propose diverse equivalence classification techniques (i.e., k-failure-equivalence and link-local-equivalence reduction) to reduce the symbolic traffic execution overhead caused by both the large size of the production WAN and the huge number of traffic flows traversing it. YU has been used in the daily verification of our WAN for several months and has successfully identified potential failure scenarios that would lead to traffic load violations. Yifei Yuan 0001, Fangdan Ye, Mengqi Liu 0001, Ruizhen Yang, Tianchen Guo, Xianlong Zeng, Chenren Xu, Dennis Cai, Ennan Zhai |
SIGCOMM | 4 |
| 2023 | Automated Verification of an In-Production DNS Authoritative EngineabstractThis paper presents DNS-V, a verification framework for our in-production DNS authoritative engine, which is the core of our DNS service. The key idea for automated verification in general is based on the layered verification principle. However, we face the challenge that our in-production DNS authoritative engine lacks modularity, more specifically, as can be seen with unclean interfaces and poor data structure encapsulation. This makes the layered verification hard to apply. To address this challenge, we propose a summarization approach that performs full-path symbolic execution to accumulate all path conditions and computation effects, and then represents a module's behavior in an abstract form as a set of input-effect pairs. In addition, for portability to future iterated versions of our DNS authoritative engine, we identify common dependency library modules that remain stable across different versions, and carefully design their abstractions to make them amenable to automated reasoning. Our framework has been successful in identifying and preventing tens of critical bugs in different versions of our DNS authoritative engine from reaching production, with a porting effort of less than one person-week. Naiqian Zheng, Mengqi Liu 0001, Yuxing Xiang, Linjian Song, Nan Wang 0041, Zhuo Liang, Dennis Cai, Ennan Zhai, Xuanzhe Liu, Xin Jin 0008 |
SOSP | 2 |
| 2022 | Cetus: Releasing P4 Programmers from the Chore of Trial and Error Compiling
Ennan Zhai, Mengqi Liu 0001, Hongqiang Harry Liu |
NSDI | 4 |
| 2022 | Meissa: scalable network testing for programmable data planesabstractEnsuring the correctness of programmable data planes is important. Testing offers comprehensive correctness checking, including detecting both code bugs and non-code bugs. However, scalability is a key challenge for testing production-scale data planes to achieve high coverage. This paper presents Meissa, a scalable network testing system for programmable data planes with full path coverage. The core of Meissa is a domain-specific code summary technique that simplifies the control flow graph of a data plane program for scalable testing without sacrificing coverage. Code summary decomposes a data plane program into individual pipelines, and summarizes each pipeline with a succinct representation. We formally prove that Meissa with code summary achieves 100% path coverage. We use both open-source and production-scale data plane programs to evaluate Meissa. The evaluation shows that (i) Meissa is able to test production-scale data plane programs that cannot be supported by state-of-the-art efforts, and (ii) besides P4 code bugs, Meissa is able to not only identify known non-code bugs, but also detect previously-unknown non-code bugs. We also share in this paper several real cases tested by Meissa in a production programmable data plane. Naiqian Zheng, Mengqi Liu 0001, Ennan Zhai, Hongqiang Harry Liu, Kaicheng Yang 0001, Xuanzhe Liu, Xin Jin 0008 |
SIGCOMM | 2 |
| 2022 | Compositional virtual timelines: verifying dynamic-priority partitions with algorithmic temporal isolationabstractReal-time systems power safety-critical applications that require strong isolation among each other. Such isolation needs to be enforced at two orthogonal levels. On the micro-architectural level, this mainly involves avoiding interference through micro-architectural states, such as cache lines. On the algorithmic level, this is usually achieved by adopting real-time partitions to reserve resources for each application. Implementations of such systems are often complex and require formal verification to guarantee proper isolation. In this paper, we focus on algorithmic isolation, which is mainly related to scheduling-induced interferences. We address earliest-deadline-first (EDF) partitions to achieve compositionality and utilization, while imposing constraints on tasks' periods and enforcing budgets on these periodic partitions to ensure isolation between each other. The formal verification of such a real-time OS kernel is challenging due to the inherent complexity of the dynamic priority assignment on the partition level. We tackle this problem by adopting a dynamically constructed abstraction to lift the reasoning of a concrete scheduler into an abstract domain. Using this framework, we verify a real-time operating system kernel with budget-enforcing EDF partitions and prove that it indeed ensures isolation between partitions. All the proofs are mechanized in Coq. Mengqi Liu 0001, Zhong Shao 0001, Hao Chen 0023, Man-Ki Yoon, Jung-Eun Kim |
Proc. ACM Program. Lang. | 1 |
| 2021 | Aquila: a practically usable verification system for production-scale programmable data planesabstractThis paper presents Aquila, the first practically usable verification system for Alibaba's production-scale programmable data planes. Aquila addresses four challenges in building a practically usable verification: (1) specification complexity; (2) verification scalability; (3) bug localization; and (4) verifier self validation. Specifically, first, Aquila proposes a high-level language that facilitates easy expression of specifications, reducing lines of specification codes by tenfold compared to the state-of-the-art. Second, Aquila constructs a sequential encoding algorithm to circumvent the exponential growth of states associated with the upscaling of data plane programs to production level. Third, Aquila adopts an automatic and accurate bug localization approach that can narrow down suspects based on reported violations and pinpoint the culprit by simulating a fix for each suspect. Fourth and finally, Aquila can perform self validation based on refinement proof, which involves the construction of an alternative representation and subsequent equivalence checking. To this date, Aquila has been used in the verification of our production-scale programmable edge networks for over half a year, and it has successfully prevented many potential failures resulting from data plane bugs. Bingchuan Tian, Mengqi Liu 0001, Ennan Zhai, Yu Zhou 0008, Mengjing Ma, Xionglie Wei, Hongqiang Harry Liu, Ming Zhang 0005, Chen Tian 0001, Minlan Yu |
SIGCOMM | 3 |
| 2021 | Blinder: Partition-Oblivious Hierarchical Scheduling
Man-Ki Yoon, Mengqi Liu 0001, Hao Chen 0023, Jung-Eun Kim, Zhong Shao 0001 |
USENIX Security Symposium | 2 |
| 2020 | Virtual timeline: a formal abstraction for verifying preemptive schedulers with temporal isolationabstractThe reliability and security of safety-critical real-time systems are of utmost importance because the failure of these systems could incur severe consequences (e.g., loss of lives or failure of a mission). Such properties require strong isolation between components and they rely on enforcement mechanisms provided by the underlying operating system (OS) kernel. In addition to spatial isolation which is commonly provided by OS kernels to various extents, it also requires temporal isolation, that is, properties on the schedule of one component (e.g., schedulability) are independent of behaviors of other components. The strict isolation between components relies critically on algorithmic properties of the concrete implementation of the scheduler, such as timely provision of time slots, obliviousness to preemption, etc. However, existing work either only reasons about an abstract model of the scheduler, or proves properties of the scheduler implementation that are not rich enough to establish the isolation between different components. In this paper, we present a novel compositional framework for reasoning about algorithmic properties of the concrete implementation of preemptive schedulers. In particular, we use virtual timeline , a variant of the supply bound function used in real-time scheduling analysis, to specify and reason about the scheduling of each component in isolation. We show that the properties proved on this abstraction carry down to the generated assembly code of the OS kernel. Using this framework, we successfully verify a real-time OS kernel, which extends mCertiKOS, a single-processor non-preemptive kernel, with user-level preemption, a verified timer interrupt handler, and a verified real-time scheduler. We prove that in the absence of microarchitectural-level timing channels, this new kernel enjoys temporal and spatial isolation on top of the functional correctness guarantee. All the proofs are implemented in the Coq proof assistant. Mengqi Liu 0001, Lionel Rieg, Zhong Shao 0001, Ronghui Gu, David Costanzo, Jung-Eun Kim, Man-Ki Yoon |
Proc. ACM Program. Lang. | 1 |
| 2019 | Integrating Formal Schedulability Analysis into a Verified OS KernelabstractFormal verification of real-time systems is attractive because these systems often perform critical operations. Unlike non real-time systems, latency and response time guarantees are of critical importance in this setting, as much as functional correctness. Nevertheless, formal verification of real-time OSes usually stops the scheduling analysis at the policy level: they only prove that the scheduler (or its abstract model) satisfies some scheduling policy. In this paper, we go further and connect together Prosa, a verified schedulability analyzer, and RT-CertiKOS, a verified single-core sequential real-time OS kernel. Thus, we get a more general and extensible schedulability analysis proof for RT-CertiKOS, as well a concrete implementation validating Prosa models. It also showcases that it is realistic to connect two completely independent formal developments in a proof assistant. Xiaojie Guo 0003, Maxime Lesourd, Mengqi Liu 0001, Lionel Rieg, Zhong Shao 0001 |
CAV (2) | 3 |
| 2019 | A new hierarchical software architecture towards safety-critical aspects of a drone systemabstractA new hierarchical software architecture is proposed to improve the safety and reliability of a safety-critical drone system from the perspective of its source code. The proposed architecture uses formal verification methods to ensure that the implementation of each module satisfies its expected design specification, so that it prevents a drone from crashing due to unexpected software failures. This study builds on top of a formally verified operating system kernel, certified kit operating system (CertiKOS). Since device drivers are considered the most important parts affecting the safety of the drone system, we focus mainly on verifying bus drivers such as the serial peripheral interface and the inter-integrated circuit drivers in a drone system using a rigorous formal verification method. Experiments have been carried out to demonstrate the improvement in reliability in case of device anomalies. Zhen-guo Yin, Zhong Shao 0001, Mengqi Liu 0001, Hao Chen 0023 |
Frontiers Inf. Technol. Electron. Eng. | 5 |