A reconfigurable mesh (RM) is the two-dimensional mesh-connected computer enhanced with a reconfigurable bus system. The bus system is used to dynamically obtain various interconnection patterns among the processors during the execution of programs. This paper shows that the RM of size n × n can be simulated in O(n2/m2 log n) steps by the RM of smaller size m × m (m

we have developed a system to support communication between students and teachers on the computer network.By using e-mail, they can exchange information, e.g., questions and reports whenever and wherever they can access the Internet.And by using W'orld lk7ide Web, the teacher can provide impressive teaching material for the student.Moreover the system provides "easy maintenance" facilities.So the teachers who use it don't have to master the details of the system.They can use it easily by following various navigational information instructions.And to use the system for many years, it can reuse information and setups which were made previously.1

In recent years there has been renewal of interest in the reorganization and transformation of classes for object-oriented design and programming. Numerous attempts have been made by researchers to find algorithms and heuristics to produce "good" and "reusable" class organizations based on the inheritance hierarchy. However, little attention has been given to the reorganization of the aggregation hierarchy which forms the part-of relationship between classes. We are concerned with the inheritance and aggregation hierarchies, and define the object semi-equivalence relation between the class hierarchies by extending the object-equivalence relation. We also present a minimal set of transformations which forms a foundation for reorganization between class hierarchies based on the object semi-equivalence. This set is proven to be correct, complete, and minimal.

Abstract Recent advances in hardware technology have made the construction of multiprocessor systems economically feasible. This paper describes a new programming language (Concurrent C) suitable for distributed systems which are networks of loosely connected processors, each with its own local storage. Concurrent C is the extended version of the programming language C, incorporating features for parallel processing and interprocess communications.

Area and computation time are considered to be important measures with which VLSI circuits are evaluated. In this paper, the area-time complexity for nontrivial n-input m-output Boolean functions, such as a decoder and an encoder, is studied with a model similar to Brent-Kung's model. A lower bound on area-time-product (ATαaα.≥1) for these functions is shown: for example, ATα= ω(2n. nα-l) for an n-input 2V-output decoder, and ATα= ω( n . logα-1n) for an n-input ⌈log n⌉-output encoder. The results shown in this paper are complementary to those by Brent-Kung or Thompson, and are useful for a class of functions of rather simple structures, e.g., a priority encoder, a comparator, and symmetric functions.

A negative gate is a gate that can realize an arbitrary negative function (or monotone decreasing function) and a positive gate is one that can realize an arbitrary positive function (or monotone increasing function). This paper discusses methods of realizing a given logical function or a given set of logical functions using a minimum number of negative gates alone or using a minimum number of negative and positive gates.

The basic properties and realization of failsafe combinational logic nets and failsafe sequential machines are discussed. The present note concerns totally asymmetric faiiure nets which are composed only of (+) elements and/ or (-) elements, where a (+) element is an asymmetric failure element which never fails to logical zero and a (-) element is defined similarly.

The following theorem is proved. Letf(x_1,\cdots, x_m)be a binary nonzero polynomial ofmvariables of degree\nu. H the number of binarym-tuples(a_1,\cdots, a_m)withf(a_1, \cdots, a_m)= 1 is less than2^{m-\nu+1}, thenfcan be reduced by an invertible affme transformation of its variables to one of the following forms. \begin{equation} f = y_1 \cdots y_{\nu - \mu} (y_{\nu-\mu+1} \cdots y_{\nu} + y_{\nu+1} \cdots y_{\nu+\mu}), \end{equation} wherem \geq \nu+\muand\nu \geq \mu \geq 3. \begin{equation} f = y_1 \cdots y_{\nu-2}(y_{\nu-1} y_{\nu} + y_{\nu+1} y_{\nu+2} + \cdots + y_{\nu+2\mu -3} y_{\nu+2\mu-2}), \end{equation} This theorem completely characterizes the codewords of the\nuth-order Reed-Muller code whose weights are less than twice the minimum weight and leads to the weight enumerators for those codewords. These weight formulas are extensions of Berlekamp and Sloane's results.

It is shown that ifm \neq 8, 12andm > 6, there are some binary primitive BCH codes (BCH codes in a narrow sense) of length2^{m} - 1whose minimum weight is greater than the BCH bound. This gives a negative answer to the question posed by Peterson [1] of whether or not the BCH bound is always the actual minimum weight of a binary primitive BCH code. It is also shown that for any evenm \geq 6, there are some binary cyclic codes of length2^{m} - 1that have more information digits than the primitive BCH codes of length2^{m} - 1with the same minimum weight.

This paper presents a systematic procedure for finding optimum error-correcting group codes for the binary symmetric channel with m check digits and a minimum distance not less than do, where m and do are given integers. Some new schemes for reducing the computing time are used. The search procedure is readily programmable for computer execution and several programs were carried out on an IBM 7044. The newly found seven optimum triple-error-correcting group codes and six optimum double-error-correcting group codes including five quasi-perfect double-error-correcting codes are tabulated. Also, a list of optimum shortened cyclic codes found by a similar procedure is presented. The efficiency of the search procedure is demonstrated by the fact that the program yielded the new codes in a fairly short time.