Early parallel architectures where shared memory systems (UMA, NUMA), which had the disadvantage of the shared memory bottleneck that limited the scalability of the system. In contrast, distributed memory architectures with message passing (NORMAs) provided any desired scalability; however, at the cost of a substantial communication latency. The latency could be reduced by custom communication hardware (examples: SUPRENUM, MANNA) yet since there was still a software routine involved, the remaining latency was in the order of microseconds. Therefore, and because of the simpler programming model of shared memory, it became the trend of the nineties to return to UMAs and NUMAs, employing powerful communication hardware to minimize the remote memory access time.

This paper presents a modeling approach based on deterministic and stochastic Petri nets (DSPN) for analyzing the performance of node architectures for MIMD multiprocessor systems with distributed memory. DSPN are a numerically solvable modeling formalism with a graphical representation. The modeling approach supports design decisions for node architectures by providing quantitative results concerning processor and memory utilization for several design alternatives. To illustrate the proposed approach, DSPN of two node architectures are presented and employed for a comparative performance study.

In order to combine the benefits of dataflow and control-flow computation while avoiding the pitfalls of both, the authors propose a two-level model of large-grain dataflow computation, called LGDG computation. A formalism has been provided in a previous paper to prove the determinism of parallel program execution under this model. The current paper presents the basic LGDG computer architecture which is organized at two levels, called the graph level and the node level. The kernel of the node-level architecture is characterized by its non-branch RISC (N-RISC) feature, which ensures an optimal utilization of pipeline processing. This kernel is supported by various co-processors based on the principle of function migration. We will show in this paper how the graph-level architecture can be reduced to a matching unit, extended by a writable control store, through node migration and node aggregation. As a result, the matching overhead is drastically reduced, thus eliminating the most severe bottleneck of existing 'fine-grain' dataflow computers.

For the sake of clarification the paper first discusses some major aspects of supercomputer technology and architecture. On this basis an outline is given of major European developments in the realm of supercomputers that happened in the second half of the eighties or are planned for the first half of the nineties. The projects discussed are: Supernode, ISIS, SUPRENUM, and GENESIS.

The next generation of supercomputers will be largely parallel MIMD architectures, ranging in peak performance from 10 to 100 GFLOPS in the mid nineties to 1000 GFLOPS in the late nineties. Largely parallel means that such a system will consist of hundreds or thousands of processing nodes (PN), and each PN will have a peak performance of several hundred MFLOPS. Obtaining such an extremely high performance is not only an issue of appropriate node architecture but requires also a very high bandwidth interconnection network and an extremely fast implementation of the inter process communication (IPC) protocol. The paper deals with an IPC protocol implementation that reduces the communication startup time to approximately 20 microseconds, by combining highly efficient software solutions, given in the form of lightweight processes, with dedicated hardware, given in the form of a specific communication processor in each PN, to perform the rendezvous required between sender and receiver processes.

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Existing taxonomies of computer architecture lack the descriptive tools to deal with the large variety of existing principles, features, and mechanisms of the existing spectrum of single processor, multi processor, and multi computer architectures. Consequently, they lack the discriminating power to be able to taxonomize computer architecture. In the paper, a new approach toward a complete taxonomy is presented. The key to the taxonomy is to start with the dichotomy of 'operational principle' and 'hardware structure' as the foundation of a computer architecture and describe the constituents of the operational principle in terms of 'machine data types' consisting of 'machine data objects', their representations, and the functions applicable on the objects. The resulting taxonomy provides a systematic approach to the design of innovative computer architectures.

An abstract view of a computer system is provided by a hierarchy of functions, ranging from the high-level operating system functions down to the primitive functions of the hardware. Vertical migration of high-level functions into the microcode of a CPU or horizontal migration of hardware functions out of the CPU into dedicated processors alone is not an adequate realization method for innovative computer architectures with complex functionality. In the paper, a new design principle called hierarchical function distribution is introduced to cope with the task of designing innovative multicomputer systems with complex functionality. The design rules of hierarchical function distribution are presented, and the advantages of the approach are discussed and illustrated by examples.

The next generation of "intelligent" industrial robots will necessitate off-line programming systems in which generative graphics (picture generation) and cognitive graphics (picture understanding) is combined. This will require programming languages that comprise graphical data types. The classical implementation of a graphical programming system in the form of a procedure package deals with representations of graphical objects and thus does not provide graphical data types. However, modern abstract data type based languages allow graphical data types to be introduced as user-defined abstract data types. The features of such a language, CLU, is discussed, and the implementation of a graphical data type in CLU is illustrated by a simple example.

Computer architectures may be characterized by their operational principle and their physical structure. The paper defines these two characteristics for the novel concept of data structure architectures (DSAs). The representation and processing of arbitrary data structures in such a DSA is demonstrated by examples. It is shown how the functional requirements of a DSA can be satisfied by the specific information structure and the physical structure of the STARLET architecture introduced in preceding publications.

The main topic of the paper is to introduce a concept for structured display programming in interactive computer graphics and to discuss the suitability of FORTRAN, ALGOL, PL/I, and APL as the host language for such a programming system. To this end, the interrelationship between picture structures, data structures, and language structures is first established. Based on the obtained conclusions, a model language for interactive display programming (GRIP) is introduced. The suitability of the above mentioned languages is discussed, and experiences with the implementation of the GRIP philosophy in some of these languages are communicated.

It is a well-acknowledged fact that the adequate structuring of data is as important as the adequate structuring of a program. The classical von Neumann - machine deals on the hardware level only with scalars and, therefore, provides no hardware support of any sort for the manipulation of more complex data structures. Some more recently developed concepts - all variants of Iliffe's Basic Language Machine -- provide some hardware support for structuring data in the form of trees. Contrastingly, in the STARLET concept to be discussed in this paper, the basic data structure is that of ordered sets (as given by strings and arrays). In the paper, the basic notions of this novel concept are introduced and discussed, especially the internal information structure which differs considerably from that of the von Neumann-machine or other concepts. This very idiosyncratic information structure has far-reaching consequences with respect to the hardware structure of the machine. Finally, a number of resulting features will be discussed and an attempt will be made to compare the computing power of STARLET with that of avon Neumann-machine with equally fast hardware.

The design methodology developed in the paper is based on an APL-like definition of logical arrays and operations on such arrays. First, the notion of a logical algorithm is introduced as a finite state automaton described by transition and output matrix. The technical realizations of such algorithms is then uniformly described as time-discrete, space-discrete, and time-space-discrete systems, and the transition of an algorithm from state-to-state (or space node-to-space node) can be explicitly formulated in a very concise way. An application of this formalism to the state reduction problem is shown. Thus the paper extends the APL-based design of logical networks beyond the area of combinational networks as developed first by Iverson.

Abstract—Block-oriented simulation languages are a powerful tool for solving simulation problems. A problem of major importance in simulation, however, is the choice of the integration formula to be employed in the integration block. Users of early simulation languages had no difficulty selecting a formula since these languages provided only a single formula. Advanced languages have a number of formulas available, but leave the choice to the user who does not have much to go by except the good names of the formulas. Difficulties which were encountered in the use of multistep formulas made formulas of the Runge-Kutta type more popular. Experience has shown that they are less critical with respect to stability. However, the computing time for a Runge-Kutta formula is considerably larger and for this reason multistep formulas, which include the predictor- corrector scheme, are still appealing.