Instead of zero-skew or assuming a fixed skew bound, we seek to produce useful skews in clock routing. This is motivated by the fact that negative skew may allow a larger timing budget for gate sizing. We construct a useful-skew tree (UST) such that the total clock and logic power (measured as a cost function) is minimized. Given a required clock period and feasible gate sizes, a set of negative and positive skew bounds are generated. The allowable skews within these bounds and feasible gate sizes form the feasible solution space of our problem. We use a merging segment perturbation procedure and a simulated annealing approach to explore various tree configurations. This is complemented by a bi-partitioning heuristic to generate appropriate connection topology and take advantage of useful skews. Experimental results have shown 11% to 22% total power reduction over previous methods of clock routing with zero-skew or single fixed skew bound and separately sizing logic gates.

Due to process, manufacturing and system operating conditions in a real environment, clock jitter is inevitable. In the presence of jitter, zero or near-zero skew are not really safe for reliable clock operations. Appropriate skew or useful skew can serve as a safety margin to guard against clock jitter. In two-phase clocking, the nonoverlapping interval of two-phase clocks provides an additional degree of freedom to improve either the clock tree cost or jitter-tolerance. We construct a two-phase jitter-tolerant useful-skew tree (JT-UST) such that the susceptibility to clock jitter and the clock tree cost is minimized. Following the Deferred-Merge Embedding (DME) framework, we use a simulated annealing approach to explore the routing topologies and embeddings. Experimental results have shown 63% to 100% reduction of jitter-prone sink pairs over previous clock routing methods while having very comparable clock tree costs.

Article Buffer insertion and sizing under process variations for low power clock distribution Share on Authors: Joe G. Xi National Semiconductor, Corp., Santa Clara, CA and Computer Engineering, University of California, Santa Cruz, Santa Cruz, CA National Semiconductor, Corp., Santa Clara, CA and Computer Engineering, University of California, Santa Cruz, Santa Cruz, CAView Profile , Wayne W. M. Dai Computer Engineering, University of California, Santa Cruz, Santa Cruz, CA Computer Engineering, University of California, Santa Cruz, Santa Cruz, CAView Profile Authors Info & Claims DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation ConferenceJanuary 1995 Pages 491–496https://doi.org/10.1145/217474.217576Online:01 January 1995Publication History 54citation550DownloadsMetricsTotal Citations54Total Downloads550Last 12 Months3Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

To achieve delay balance, instead of making the faster path slower by elongating branches, we make slower paths faster by sizing. Given a general clock network, which may includes loops, together with a set of feasible widths for each branch, we formulate the optimal sizing of the clock network as a constrained optimization problem. By turning the skew minimization problem into a least-squares estimation problem, a modified Gauss-Marquardt's method is used to determine the optimal widths. An efficient initial sizing algorithm is proposed to speed up the sizing process. Instead of using zero-order delay model (path length) or one-order delay model (Elmore delay), we employ a generalized delay model which can handle general RLC and transmission line networks. Experimental results show that this method significantly reduces both the clock skew and path delays from source to terminals.